Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Bring F3xD4 (Clock/Power Control Register 0) more in line with BKDG i more cases. It requires looking at the CPU package type so I add a function for that (in the wrong place?) and some new constants Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -179,16 +179,51 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
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pci_write_config32(dev, 0xd8, dtemp);
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}
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static u32 power_up_down(int node) {
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static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
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u8 link0isGen3 = 0;
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u8 offset;
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if (AMD_CpuFindCapability(node, 0, &offset)) {
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link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
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}
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/* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
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S1g3 in link Gen3 mode, but I don't know how to tell
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package S1g3 from S1g4 */
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if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
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&& link0isGen3) {
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return 5 ; /* divide clk by 128*/
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} else {
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return 4 ; /* divide clk by 16 */
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}
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}
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static u32 power_up_down(int node, u8 procPkg) {
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u32 dword=0;
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/* check platform type */
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if (!(get_platform_type() & AMD_PTYPE_SVR)) {
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/* For non-server platform
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* PowerStepUp=01000b - 50nS
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* PowerStepDown=01000b - 50ns
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*/
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dword |= PW_STP_UP50 | PW_STP_DN50 ;
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/* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
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u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
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|| (procPkg == AMD_PKGTYPE_S1gX)
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|| (procPkg == AMD_PKGTYPE_ASB2));
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if (singleLinkFlag) {
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/*
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* PowerStepUp=01000b - 50nS
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* PowerStepDown=01000b - 50ns
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*/
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dword |= PW_STP_UP50 | PW_STP_DN50;
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} else {
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u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
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u32 isocEn = 0;
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int j;
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for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
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u8 offset;
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if (AMD_CpuFindCapability(node, j, &offset)) {
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isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
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}
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}
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if (dispRefModeEn || isocEn) {
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dword |= PW_STP_UP50 | PW_STP_DN50 ;
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} else {
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/* get number of cores for PowerStepUp & PowerStepDown in server
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1 core - 400nS - 0000b
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2 cores - 200nS - 0010b
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@ -210,28 +245,31 @@ static u32 power_up_down(int node) {
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dword |= PW_STP_UP100 | PW_STP_DN100;
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break;
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}
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}
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}
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return dword;
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}
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static void config_clk_power_ctrl_reg0(int node) {
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static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
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device_t dev = NODE_PCI(node, 3);
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/* Program fields in Clock Power/Control register0 (F3xD4) */
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/* set F3xD4 Clock Power/Timing Control 0 Register
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* NbClkDidApplyAll=1b
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* NbClkDid=100b
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* NbClkDid=100b or 101b
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* PowerStepUp= "platform dependent"
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* PowerStepDown= "platform dependent"
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* LinkPllLink=01b
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* ClkRampHystSel=HW default
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* ClkRampHystCtl=HW default
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* ClkRampHystSel=1111b
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*/
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u32 dword= pci_read_config32(dev, 0xd4);
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dword &= CPTC0_MASK;
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dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; /* per BKDG */
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dword |= power_up_down(node);
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dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
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dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
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dword |= power_up_down(node, procPkg);
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pci_write_config32(dev, 0xd4, dword);
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@ -296,13 +334,15 @@ static void prep_fid_change(void)
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for (i = 0; i < nodes; i++) {
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printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
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dev = NODE_PCI(i, 3);
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u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
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u8 procPkg = mctGetProcessorPackageType();
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setVSRamp(dev);
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/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
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/* Figure out the value for VsSlamTime and program it */
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recalculateVsSlamTimeSettingOnCorePre(dev);
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config_clk_power_ctrl_reg0(i);
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config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
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config_power_ctrl_misc_reg(dev);
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@ -214,6 +214,11 @@ u32 mctGetLogicalCPUID(u32 Node)
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return ret;
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}
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static u8 mctGetProcessorPackageType(void) {
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/* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
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u32 BrandId = cpuid_ebx(0x80000001);
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return (u8)((BrandId >> 28) & 0x0F);
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}
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static void raminit_amdmct(struct sys_info *sysinfo)
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{
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@ -111,6 +111,7 @@
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#define NB_FID_EN 0x20 /* NbFidEn bit ON */
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#define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */
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#define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */
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#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */
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#define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */
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#define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/
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#define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */
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@ -119,6 +120,11 @@
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#define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/
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#define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */
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#define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/
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#define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp
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hysteresis select. BIOS
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should program
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F3xC4[ClkRampHystSel] to
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1111b */
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#define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */
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@ -134,3 +134,13 @@
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#define DC_CFG 0xC0011022
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#define BU_CFG 0xC0011023
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#define BU_CFG2 0xC001102A
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/*
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* Processor package types
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*/
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#define AMD_PKGTYPE_FrX_1207 0
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#define AMD_PKGTYPE_AM3_2r2 1
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#define AMD_PKGTYPE_S1gX 2
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#define AMD_PKGTYPE_G34 3
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#define AMD_PKGTYPE_ASB2 4
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#define AMD_PKGTYPE_C32 5
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