diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index ea6ac8234b..0188e70b05 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -465,6 +465,9 @@ struct soc_intel_elkhartlake_config {
 
 	/* Disable L1 prefetcher */
 	bool L1_prefetcher_disable;
+
+	/* Activate real time tuning according to the Real-Time Tuning Guide (doc #640979) */
+	bool realtime_tuning_enable;
 };
 
 typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 1466ee21a2..8d802f42be 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -307,10 +307,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 */
 	params->EnableTcoTimer = 1;
 
-	/* PCH Master Gating Control */
-	params->PchPostMasterClockGating = 1;
-	params->PchPostMasterPowerGating = 1;
-
+	/* Set up recommended real time parameters if real time tuning is enabled. */
+	if (config->realtime_tuning_enable) {
+		params->PchPostMasterClockGating = 0;
+		params->PchPostMasterPowerGating = 0;
+		params->PchPwrOptEnable = 0;
+		params->PsfTccEnable = 1;
+		params->PmcLpmS0ixSubStateEnableMask = 0;
+		params->PchDmiAspmCtrl = 0;
+		params->PchLegacyIoLowLatency = 0;
+		params->EnableItbm = 0;
+		params->D3ColdEnable = 0;
+		params->PmcOsIdleEnable = 0;
+	} else {
+		params->PchPostMasterClockGating = 1;
+		params->PchPostMasterPowerGating = 1;
+	}
 	/* HECI */
 	params->Heci3Enabled = config->Heci3Enable;
 
@@ -360,6 +372,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
 		/* Virtual Channel 1 to Traffic Class mapping */
 		params->PcieRpVc1TcMap[i] = 0x60;
+		if (config->realtime_tuning_enable)
+			params->PcieRpEnableCpm[i] = 0;
 	}
 
 	/* SATA config */
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index d2d118a793..ad3846ec1e 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -61,8 +61,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
 
 	/* PCH Master Gating Control */
-	m_cfg->PchMasterClockGating = 1;
-	m_cfg->PchMasterPowerGating = 1;
+	if (config->realtime_tuning_enable) {
+		m_cfg->PchMasterClockGating = 0;
+		m_cfg->PchMasterPowerGating = 0;
+		m_cfg->DisPgCloseIdleTimeout = 0;
+		m_cfg->PowerDownMode = 0;
+	} else {
+		m_cfg->PchMasterClockGating = 1;
+		m_cfg->PchMasterPowerGating = 1;
+	}
 
 	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);