mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun

Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.

It needs to confirm the PCIe Signal Integrity after enabled.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
Chris.Wang 2023-01-04 10:15:00 +08:00 committed by Martin L Roth
parent 81016b5c24
commit adec2e6c45
1 changed files with 3 additions and 0 deletions

View File

@ -99,6 +99,9 @@ chip soc/amd/mendocino
register "stt_skin_temp_apu_F" = "0x3200"
device domain 0 on
register "dxio_tx_vboost_enable" = "1"
device ref gpp_bridge_1 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device