GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/haswell/romstage.c: Align pei_data initializers 

Aligned initializers should be easier to read.

Change-Id: If9238177c4959d80444fc842fd83794bfdac5c4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Angel Pons 2020-07-04 01:38:03 +02:00
parent 8aab7876d1
commit ae0eeb2ab6
1 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/northbridge/intel/haswell/romstage.c
View File

@ -46,25 +46,25 @@ void mainboard_romstage_entry(void)
int wake_from_s3; int wake_from_s3;
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR, .mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE, .smbusbar = SMBUS_IO_BASE,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA, .rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,
.system_type = get_pch_platform_type(), .system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE, .tseg_size = CONFIG_SMM_TSEG_SIZE,
.ec_present = cfg->ec_present, .ec_present = cfg->ec_present,
.gbe_enable = gbe && gbe->enabled, .gbe_enable = gbe && gbe->enabled,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
.dq_pins_interleaved = cfg->dq_pins_interleaved, .dq_pins_interleaved = cfg->dq_pins_interleaved,
.max_ddr3_freq = 1600, .max_ddr3_freq = 1600,
.usb_xhci_on_resume = cfg->usb_xhci_on_resume, .usb_xhci_on_resume = cfg->usb_xhci_on_resume,
}; };
mainboard_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data);