soc/cavium/cn81xx: Set cntfrq_el0

Set cntfrq_el0 to provide correct timer frequency.

Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25450
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/cavium/cn8100_sff_evb/mainboard.c

@@ -88,6 +88,9 @@ static void mainboard_init(struct device *dev)
 		if (!uart_is_enabled(i))
 			uart_setup(i, 0);
 	}
+
+	/* Init timer */
+	soc_timer_init();
 }
 
 static void mainboard_enable(struct device *dev)

src/soc/cavium/cn81xx/include/soc/timer.h

@@ -27,4 +27,7 @@ void watchdog_poke(const size_t index);
 void watchdog_disable(const size_t index);
 int watchdog_is_running(const size_t index);
 
+/* Timer functions */
+void soc_timer_init(void);
+
 #endif	/* __SOC_CAVIUM_CN81XX_TIMER_H__ */

src/soc/cavium/cn81xx/timer.c

@@ -25,6 +25,7 @@
 #include <timer.h>
 #include <soc/addressmap.h>
 #include <assert.h>
+#include <arch/clock.h>
 
 /* Global System Timers Unit (GTI) registers */
 struct cn81xx_timer {
@@ -97,6 +98,9 @@ void timer_monotonic_get(struct mono_time *mt)
 	mono_time_set_usecs(mt, timer_raw_value());
 }
 
+/* Setup counter to operate at 1MHz */
+static const size_t tickrate = 1000000;
+
 /**
  * Init Global System Timers Unit (GTI).
  * Configure timer to run at 1MHz tick-rate.
@@ -114,8 +118,6 @@ void init_timer(void)
 	/* Use coprocessor clock source */
 	write32(&gti->cc_imp_ctl, 0);
 
-	/* Setup counter to operate at 1MHz */
-	const size_t tickrate = 1000000;
 	write32(&gti->cc_cntfid0, tickrate);
 	write32(&gti->ctl_cntfrq, tickrate);
 	write32(&gti->cc_cntrate, ((1ULL << 32) * tickrate) / sclk);
@@ -127,6 +129,11 @@ void init_timer(void)
 	//BDK_MSR(CNTPS_CTL_EL1, u);
 }
 
+void soc_timer_init(void)
+{
+	set_cntfrq(tickrate);
+}
+
 /**
  * Setup the watchdog to expire in timeout_ms milliseconds. When the watchdog
  * expires, the chip three things happen: