helios: Add TEMP_SENSOR4 to DPTF
Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to the DPTF. BRANCH=None BUG=b:142266102 TEST=`emerge-hatch coreboot` Verify that Helios builds correctly. Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
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@ -54,6 +54,17 @@
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#define DPTF_TSR2_ACTIVE_AC4 40
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#define DPTF_TSR2_ACTIVE_AC4 40
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#define DPTF_TSR2_ACTIVE_AC5 38
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#define DPTF_TSR2_ACTIVE_AC5 38
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#define DPTF_TSR3_SENSOR_ID 3
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#define DPTF_TSR3_SENSOR_NAME "CPU"
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#define DPTF_TSR3_PASSIVE 85
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#define DPTF_TSR3_CRITICAL 100
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#define DPTF_TSR3_ACTIVE_AC0 0
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#define DPTF_TSR3_ACTIVE_AC1 0
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#define DPTF_TSR3_ACTIVE_AC2 0
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#define DPTF_TSR3_ACTIVE_AC3 0
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#define DPTF_TSR3_ACTIVE_AC4 0
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#define DPTF_TSR3_ACTIVE_AC5 0
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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#define DPTF_ENABLE_FAN_CONTROL
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@ -107,6 +118,10 @@ Name (DART, Package () {
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Package () {
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0,
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0, 0, 0
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0,
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0, 0, 0
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}
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}
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})
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})
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@ -122,6 +137,9 @@ Name (DTRT, Package () {
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/* CPU Throttle Effect on TSR2 */
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/* CPU Throttle Effect on TSR2 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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/* CPU Throttle Effect on TSR3 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
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})
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})
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Name (MPPC, Package ()
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Name (MPPC, Package ()
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