From ae20d4c78f9fbb5fe9f8c1ef026e159961968f73 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 24 Aug 2021 00:38:39 -0700 Subject: [PATCH] mb/google/volteer: Fix USB4 enabling for volteer family volteer baseboard was currently enabling TBT(USB4) devices in baseboard devicetree and also selecting the Kconfigs required for resource allocation above 4G for the USB4 controllers. However, not all volteer devices have USB4 support. This change fixes USB4 enabling for volteer family by making the following udpates: 1. TBT devices are moved from baseboard devicetree to individual override trees for the variants that actually support USB4. 2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as on instead of hidden for all variants other than volteer reference. This is because volteer reference is the only device that has an asymmetric support for USB4 (i.e. does not support USB4 on C0 port). 3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for these variants. Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112 Reviewed-by: Weimin Wu Reviewed-by: Nick Vaccaro Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 5 +-- src/mainboard/google/volteer/Kconfig.name | 6 ++++ .../volteer/variants/baseboard/devicetree.cb | 15 -------- .../volteer/variants/copano/overridetree.cb | 18 +++++++--- .../volteer/variants/lindar/overridetree.cb | 5 --- .../volteer/variants/malefor/overridetree.cb | 5 --- .../volteer/variants/volteer/overridetree.cb | 16 +++++++++ .../volteer/variants/volteer2/overridetree.cb | 17 +++++++++ .../volteer/variants/voxel/overridetree.cb | 36 ++++++++++--------- 9 files changed, 75 insertions(+), 48 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 73fe6c7142..3425a1981c 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -106,8 +106,7 @@ config MAINBOARD_PART_NUMBER default "Volet" if BOARD_GOOGLE_VOLET default "Chronicler" if BOARD_GOOGLE_CHRONICLER -config PCIEXP_HOTPLUG - default y +if PCIEXP_HOTPLUG # Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) # Revision 0.7.6 Section 7.2.5.1.5 @@ -123,6 +122,8 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM hex default 0x1c000000 # 448 MiB +endif # PCIEXP_HOTPLUG + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index c483cc9d12..49fc8f3f68 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -46,6 +46,7 @@ config BOARD_GOOGLE_VOLTEER select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select INTEL_CAR_NEM + select PCIEXP_HOTPLUG config BOARD_GOOGLE_VOLTEER2 bool "-> Volteer2" @@ -53,6 +54,7 @@ config BOARD_GOOGLE_VOLTEER2 select VARIANT_HAS_MIPI_CAMERA select DRIVERS_GENESYSLOGIC_GL9755 select DRIVER_I2C_TPM_ACPI + select PCIEXP_HOTPLUG # Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board config BOARD_GOOGLE_VOLTEER2_TI50 @@ -61,11 +63,13 @@ config BOARD_GOOGLE_VOLTEER2_TI50 select VARIANT_HAS_MIPI_CAMERA select DRIVERS_GENESYSLOGIC_GL9755 select DRIVER_I2C_TPM_ACPI + select PCIEXP_HOTPLUG config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select PCIEXP_HOTPLUG config BOARD_GOOGLE_ELEMI bool "-> Elemi" @@ -80,10 +84,12 @@ config BOARD_GOOGLE_DROBIT bool "-> Drobit" select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 + select PCIEXP_HOTPLUG config BOARD_GOOGLE_COPANO bool "-> Copano" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select PCIEXP_HOTPLUG config BOARD_GOOGLE_COLLIS bool "-> Collis" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index dd24779cca..66fb568f9f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -457,21 +457,6 @@ chip soc/intel/tigerlake device generic 0 on end end end # DPTF 0x9A03 - # Volteer reference design does not have PCIe on Type-C port C0 so it should - # not have hotplug resources allocated. Marking the device hidden will ensure - # it is still enabled so it can participate in power management. - device ref tbt_pcie_rp0 hidden - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 - end - device ref tbt_pcie_rp1 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 - end - device ref tbt_dma0 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 - end device ref gna on end device ref north_xhci on end device ref south_xhci on end diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 3580c6b86b..f22a6c17c8 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -102,6 +102,19 @@ chip soc/intel/tigerlake device generic 0 on end end end + + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -204,11 +217,6 @@ chip soc/intel/tigerlake device generic 0 on end end end - # This variant has USB4/PCIe on both ports so RP0 must be enabled - # in order for hotplug resources to be assigned to Type-C Port C0. - device ref tbt_pcie_rp0 on - probe DB_USB USB4_GEN3 - end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 3a0f14833e..b1a9662a76 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -175,11 +175,6 @@ chip soc/intel/tigerlake end end end - # Baseboard has these on, so they must be disabled here. - device ref tbt_pcie_rp0 off end - device ref tbt_pcie_rp1 off end - device ref tbt_dma0 off end - device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index f1f86b9e1b..c9772db6b5 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -25,11 +25,6 @@ chip soc/intel/tigerlake }" device domain 0 on - # Baseboard has these on, so they must be disabled here. - device ref tbt_pcie_rp0 off end - device ref tbt_pcie_rp1 off end - device ref tbt_dma0 off end - device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index a4702a2b2c..f3b7549e82 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -47,6 +47,22 @@ chip soc/intel/tigerlake register "HybridStorageMode" = "1" device domain 0 on + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref ipu on end device ref i2c0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 8fc4d7b4a9..2654bd7a69 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -100,6 +100,23 @@ chip soc/intel/tigerlake device generic 0 on end end end + + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref ipu on end # IPU 0x9A19 device ref i2c0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 7eabfa4d4a..69d1206fda 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -69,6 +69,26 @@ chip soc/intel/tigerlake device generic 0 on end end end + + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[1].typec_port + device generic 0 on end + end + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -211,22 +231,6 @@ chip soc/intel/tigerlake device generic 0 on end end end - # This variant has USB4/PCIe on both ports so RP0 must be enabled - # in order for hotplug resources to be assigned to Type-C Port C0. - device ref tbt_pcie_rp0 on - probe DB_USB USB4_GEN3 - end - device ref tbt_dma0 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" - register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" - use tcss_usb3_port3 as dfp[0].typec_port - use tcss_usb3_port2 as dfp[1].typec_port - device generic 0 on end - end - end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.