mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`
Functional changes were already done in 5eb81bed2e
(sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
0db6e7569d
commit
ae317695e3
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@ -50,7 +50,6 @@ chip northbridge/intel/i945
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register "gpe0_en" = "0"
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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@ -54,7 +54,7 @@ chip northbridge/intel/i945
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register "gpe0_en" = "0x00800106"
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register "alt_gp_smi_en" = "0x0100"
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register "ide_legacy_combined" = "0x1"
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register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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@ -73,7 +73,6 @@ chip northbridge/intel/i945
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register "gpe0_en" = "0"
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "c3_latency" = "85"
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@ -45,7 +45,6 @@ chip northbridge/intel/x4x # Northbridge
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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register "ide_legacy_combined" = "0x0" # Combined mode broken
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ports_implemented" = "0x3"
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@ -33,7 +33,6 @@ chip northbridge/intel/i945
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "1"
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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@ -47,7 +47,6 @@ chip northbridge/intel/i945
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register "gpi13_routing" = "1"
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register "gpe0_en" = "0x20000601"
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "c3_latency" = "85"
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@ -33,7 +33,7 @@ chip northbridge/intel/i945
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "1"
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register "ide_legacy_combined" = "0x1"
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register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x1"
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register "c3_latency" = "85"
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@ -58,7 +58,7 @@ chip northbridge/intel/i945
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register "docking_supported" = "1"
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register "p_cnt_throttling_supported" = "1"
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register "ide_legacy_combined" = "0x1"
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register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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@ -68,7 +68,6 @@ struct southbridge_intel_i82801gx_config {
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uint16_t alt_gp_smi_en;
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/* IDE configuration */
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uint32_t ide_legacy_combined;
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uint32_t ide_enable_primary;
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uint32_t ide_enable_secondary;
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enum sata_mode sata_mode;
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