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baytrail: pcie: Root port initialization 

Add PCIe driver to initialize root ports.

BUG=chrome-os-partner:24111
TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to
detect networks.
BRANCH=None.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12
Reviewed-on: https://chromium-review.googlesource.com/177652
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4981
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2013-11-22 14:16:49 -06:00 committed by Kyösti Mälkki
parent 5f5cd72a55
commit ae31f7dcc4
4 changed files with 334 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/baytrail/Makefile.inc
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@ -42,6 +42,7 @@ ramstage-y += lpe.c
ramstage-y += scc.c
ramstage-y += emmc.c
ramstage-y += lpss.c
ramstage-y += pcie.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c

102
src/soc/intel/baytrail/baytrail/pcie.h Normal file
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@ -0,0 +1,102 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _BAYTRAIL_PCIE_H_
#define _BAYTRAIL_PCIE_H_
/* PCIe root port config space registers. */
#define XCAP 0x40
# define SI (1 << 24)
#define DCAP 0x44
# define MPS_MASK 0x7
#define DCTL_DSTS 0x48
# define URE (1 << 3)
# define FEE (1 << 2)
# define NFE (1 << 1)
# define CEE (1 << 0)
#define LCAP 0x4c
# define L1EXIT_SHIFT 15
# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT)
#define LCTL 0x50
# define CCC (1 << 6)
# define RL (1 << 5)
# define LD (1 << 4)
#define LSTS 0x52
#define SLCAP 0x54
# define SLN_SHIFT 19
# define SLS_SHIFT 15
# define SLV_SHIFT 7
# define HPC (1 << 6)
# define HPS (1 << 5)
#define SLCTL_SLSTS 0x58
# define PDS (1 << 22)
#define DCAP2 0x64
# define OBFFS (0x3 << 18)
# define LTRMS (1 << 11)
#define DSTS2 0x68
# define OBFFEN (3 << 13)
# define LTRME (1 << 10)
# define CTD (1 << 4)
#define CHCFG 0xd0
# define UPSD (1 << 24)
# define UNRS (1 << 15)
# define UPRS (1 << 14)
#define MPC2 0xd4
# define IPF (1 << 11)
# define LSTP (1 << 6)
# define EOIFD (1 << 1)
#define MPC 0xd8
# define CCEL_SHIFT 15
# define CCEL_MASK (0x7 << CCEL_SHIFT)
#define RPPGEN 0xe0
# define RPSCGEN (1 << 15)
# define LCLKREQEN (1 << 13)
# define BBCLKREQEN (1 << 12)
# define SRDLCGEN (1 << 11)
# define SRDBCGEN (1 << 10)
# define RPDLCGEN (1 << 9)
# define RPDBCGEN (1 << 8)
#define PWRCTL 0xe8
# define RPL1SQPOL (1 << 1)
# define RPDTSQPOL (1 << 0)
#define PHYCTL2_IOSFBCTL 0xf4
# define PLL_OFF_EN (1 << 8)
# define TDFT (3 << 14)
# define TXCFGCHWAIT (3 << 12)
# define SIID (3 << 26)
#define STRPFUSECFG 0xfc
# define LANECFG_SHIFT 14
# define LANECFG_MASK (0x3 << LANECFG_SHIFT)
#define AERCH 0x100
#define NFTS 0x314
#define L0SC 0x318
#define CFG2 0x320
# define CSREN (1 << 22)
# define LATGC_SHIFT 6
# define LATGC_MASK (0x7 << LATGC_SHIFT)
#define PCIEDBG 0x324
# define SPCE (1 << 5)
#define PCIESTS1 0x328
#define PCIEALC 0x338
#define RTP 0x33c
#define PHYCTL4 0x408
# define SQDIS (1 << 27)
#endif /* _BAYTRAIL_PCIE_H_ */

1
src/soc/intel/baytrail/chip.h
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@ -29,6 +29,7 @@ struct soc_intel_baytrail_config {
uint8_t sata_port_map;
uint8_t sata_ahci;
uint8_t ide_legacy_combined;
uint8_t clkreq_enable;
/* USB Port Disable mask */
uint16_t usb2_port_disable_mask;

230
src/soc/intel/baytrail/pcie.c Normal file
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@ -0,0 +1,230 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <reg_script.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pcie.h>
#include <baytrail/ramstage.h>
#include "chip.h"
static int pll_en_off;
static uint32_t strpfusecfg;
static inline int root_port_offset(device_t dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
static inline int is_first_port(device_t dev)
{
return root_port_offset(dev) == PCIE_PORT1_FUNC;
}
static const struct reg_script init_static_before_exit_latency[] = {
/* Disable optimized buffer flush fill and latency tolerant reporting */
REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0),
REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0),
/* Set maximum payload size. */
REG_PCI_RMW32(DCAP, ~MPS_MASK, 0),
/* Disable transmit datapath flush timer, clear transmit config change
* wait time, clear sideband interface idle counter. */
REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0),
REG_SCRIPT_END,
};
static const struct reg_script init_static_after_exit_latency[] = {
/* Set common clock configuration. */
REG_PCI_OR16(LCTL, CCC),
/* Set NFTS to 0x743a361b */
REG_PCI_WRITE32(NFTS, 0x743a361b),
/* Set common clock latency to 0x3 */
REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)),
/* Set relay timer policy. */
REG_PCI_RMW32(RTP, 0xff000000, 0x854c74),
/* Set IOSF packet fast transmit mode and link speed training policy. */
REG_PCI_OR16(MPC2, IPF | LSTP),
/* Channel configuration - enable upstream posted split, set non-posted
* and posted request size */
REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS),
/* Completion status replay enable and set TLP grant count */
REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)),
/* Assume no IOAPIC behind root port -- disable EOI forwarding. */
REG_PCI_OR16(MPC2, EOIFD),
/* Expose AER */
REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)),
/* set completion timeout to 160ms to 170ms */
REG_PCI_RMW16(DSTS2, ~CTD, 0x6),
/* Enable AER */
REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE),
/* Read and write back capabaility registers. */
REG_PCI_OR32(0x34, 0),
REG_PCI_OR32(0x80, 0),
/* Retrain the link. */
REG_PCI_OR16(LCTL, RL),
REG_SCRIPT_END,
};
static void byt_pcie_init(device_t dev)
{
struct reg_script init_script[] = {
REG_SCRIPT_SET_DEV(dev),
REG_SCRIPT_NEXT(init_static_before_exit_latency),
/* Exit latency configuration based on
* PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
REG_PCI_RMW32(LCAP, ~L1EXIT_MASK,
2 << (L1EXIT_MASK + pll_en_off)),
REG_SCRIPT_NEXT(init_static_after_exit_latency),
/* Disable hot plug, set power to 10W, set slot number. */
REG_PCI_RMW32(SLCAP, ~(HPC | HPS),
(1 << SLS_SHIFT) | (100 << SLV_SHIFT) |
(root_port_offset(dev) << SLN_SHIFT)),
/* Dynamic clock gating. */
REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN),
REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL),
REG_PCI_OR32(PCIEDBG, SPCE),
REG_SCRIPT_END,
};
reg_script_run(init_script);
if (is_first_port(dev)) {
struct soc_intel_baytrail_config *config = dev->chip_info;
uint32_t reg = pci_read_config32(dev, RPPGEN);
reg |= SRDLCGEN | SRDBCGEN;
if (config && config->clkreq_enable)
reg |= LCLKREQEN | BBCLKREQEN;
pci_write_config32(dev, RPPGEN, reg);
}
}
static const struct reg_script no_dev_behind_port[] = {
REG_PCI_OR32(PCIEALC, (1 << 26)),
REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000),
REG_PCI_OR32(PHYCTL4, SQDIS),
REG_SCRIPT_END,
};
static void check_port_enabled(device_t dev)
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
switch (root_port_offset(dev)) {
case PCIE_PORT1_FUNC:
/* Port 1 cannot be disabled from strapping config. */
break;
case PCIE_PORT2_FUNC:
/* Port 2 disabled in all configs but 4x1. */
if (rp_config != 0x0)
dev->enabled = 0;
break;
case PCIE_PORT3_FUNC:
/* Port 3 disabled only in 1x4 config. */
if (rp_config == 0x3)
dev->enabled = 0;
break;
case PCIE_PORT4_FUNC:
/* Port 4 disabled in 1x4 and 2x2 config. */
if (rp_config >= 0x2)
dev->enabled = 0;
break;
}
}
static void check_device_present(device_t dev)
{
struct reg_script no_dev[] = {
REG_SCRIPT_SET_DEV(dev),
REG_SCRIPT_NEXT(no_dev_behind_port),
REG_SCRIPT_END,
};
/* Set slot implemented. */
pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
/* No device present. */
if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) {
printk(BIOS_DEBUG, "No PCIe device present.\n");
reg_script_run(no_dev);
dev->enabled = 0;
} else if(!dev->enabled) {
/* Port is disabled, but device present. Disable link. */
pci_write_config32(dev, LCTL,
pci_read_config32(dev, LCTL) | LD);
}
}
static void byt_pcie_enable(device_t dev)
{
if (is_first_port(dev)) {
uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
pll_en_off = !!(reg & PLL_OFF_EN);
strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
}
/* Check if device is enabled in strapping. */
check_port_enabled(dev);
/* Determine if device is behind port. */
check_device_present(dev);
southcluster_enable_dev(dev);
}
static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
{
uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
if (!didvid)
didvid = pci_read_config32(dev, PCI_VENDOR_ID);
pci_write_config32(dev, 0x94, didvid);
}
static struct pci_operations pcie_root_ops = {
.set_subsystem = &pcie_root_set_subsystem,
};
static struct device_operations device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = byt_pcie_init,
.scan_bus = pciexp_scan_bridge,
.enable = byt_pcie_enable,
.ops_pci = &pcie_root_ops,
};
static const unsigned short pci_device_ids[] = {
PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID,
0
};
static const struct pci_driver pcie_root_ports __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};