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soc/intel/cannonlake: Remove depreciated UPD selection 

Several FSP silicon init UPD have been moved to memory init stage, modify
the coreboot accordingly. The UPDs below are affected:
    SkipMpInit
    VtdBaseAddress
    VtdDisable
    X2ApicOptOut

BUG=N/A
TEST=Build pass with FSP revision 7.0.47.50.

Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29260
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-10-24 17:10:56 -07:00 committed by Patrick Georgi
parent 22e0c560bb
commit ae4eee17dd
1 changed files with 0 additions and 5 deletions
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5
src/soc/intel/cannonlake/fsp_params.c
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@ -67,7 +67,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
@ -203,16 +202,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
params->SkipMpInit = !chip_get_fsp_mp_init();
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Vt-D config */
tconfig->VtdDisable = config->VtdDisable;
}
/* Mainboard GPIO Configuration */