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mb/lenovo/t440p: Factor out common MRC settings 

There's no need to redefine common settings.

Change-Id: I43922b2a1fdf90aa5004a43a17e9bc53337d88c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons 2020-07-03 18:41:35 +02:00
parent de34168436
commit ae4fb10240
1 changed files with 42 additions and 46 deletions
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88
src/mainboard/lenovo/t440p/romstage.c
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@ -45,52 +45,48 @@ void mb_late_romstage_setup(void)
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
struct pei_data mainboard_pei_data = { pei_data->system_type = 0; /* Mobile */
.pei_version = PEI_VERSION, pei_data->spd_addresses[0] = 0xa0;
.mchbar = (uintptr_t)DEFAULT_MCHBAR, pei_data->spd_addresses[2] = 0xa2;
.dmibar = (uintptr_t)DEFAULT_DMIBAR, pei_data->ec_present = 1;
.epbar = DEFAULT_EPBAR, pei_data->gbe_enable = 1;
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, /*
.smbusbar = SMBUS_IO_BASE, * 0 = leave channel enabled
.hpet_address = HPET_ADDR, * 1 = disable dimm 0 on channel
.rcba = (uintptr_t)DEFAULT_RCBA, * 2 = disable dimm 1 on channel
.pmbase = DEFAULT_PMBASE, * 3 = disable dimm 0+1 on channel
.gpiobase = DEFAULT_GPIOBASE, */
.temp_mmio_base = 0xfed08000, pei_data->dimm_channel0_disabled = 2;
.system_type = 0, /* mobile */ pei_data->dimm_channel1_disabled = 2;
.tseg_size = CONFIG_SMM_TSEG_SIZE, pei_data->max_ddr3_freq = 1600;
.spd_addresses = { 0xa0, 0, 0xa2, 0 },
.ec_present = 1, struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
.gbe_enable = 1, /* Length, Enable, OCn#, Location */
.dimm_channel0_disabled = 2, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
.dimm_channel1_disabled = 2, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
.max_ddr3_freq = 1600, { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */
.usb2_ports = { { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
/* Length, Enable, OCn#, Location */ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */
{ 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL }, { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL }, { 0x0080, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL }, { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */
{ 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
{ 0x0080, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
},
.usb3_ports = {
{ 1, 0 },
{ 1, 0 },
{ 1, USB_OC_PIN_SKIP },
{ 1, USB_OC_PIN_SKIP },
{ 1, 1 },
{ 1, 1 }, /* WWAN */
},
}; };
*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, USB_OC_PIN_SKIP },
{ 1, USB_OC_PIN_SKIP },
{ 1, 1 },
{ 1, 1 }, /* WWAN */
};
memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
} }