mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador. BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu
Nick Vaccaro
parent
887c1f1daf
commit
ae5679366b
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@ -1,23 +1,225 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <variant/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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static const struct pad_config override_gpio_table[] = {
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/* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_A13, 1, DEEP),
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/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A18 : DDSP_HPDB ==> HDMI_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
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PAD_CFG_GPO(GPP_A22, 1, DEEP),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
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/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
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PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
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PAD_NC(GPP_B23, DN_20K),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, DN_20K),
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/* C3 : SML0CLK ==> USB4_SMB_SCL */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* C4 : SML0DATA ==> USB4_SMB_SDA */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
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PAD_NC(GPP_C5, DN_20K),
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/* C7 : SML1DATA ==> EN_USI_CHARGE */
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PAD_CFG_GPO(GPP_C7, 1, DEEP),
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/* C10 : UART0_RTS# ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
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PAD_CFG_GPO(GPP_C13, 1, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* C20 : UART2_RXD ==> FPMCU_INT_L */
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PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */
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PAD_CFG_GPI(GPP_D0, NONE, DEEP),
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/* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
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PAD_CFG_GPI(GPP_D1, NONE, DEEP),
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/* D2 : ISH_GP2 ==> ISH_LID_OPEN */
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PAD_CFG_GPI(GPP_D2, NONE, DEEP),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
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PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
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/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
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PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
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/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
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/* E3 : CPU_GP0 ==> USI_REPORT_EN */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : CPU_GP1 ==> USI_INT */
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
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/* E10 : SPI1_CS# ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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/* E13 : SPI1_MOSI_IO0 ==> NC */
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PAD_NC(GPP_E13, NONE),
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/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
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/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E16, 1, DEEP),
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/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
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/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
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/* F7 : GPPF7_STRAP */
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PAD_NC(GPP_F7, DN_20K),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_F12, 1, DEEP),
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/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
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PAD_CFG_GPO(GPP_F13, 1, DEEP),
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/* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_F16, 1, DEEP),
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/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F17, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_F18, 1, DEEP),
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/* H0 : GPPH0_BOOT_STRAP1 */
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PAD_NC(GPP_H0, DN_20K),
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/* H1 : GPPH1_BOOT_STRAP2 */
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PAD_NC(GPP_H1, DN_20K),
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/* H2 : GPPH2_BOOT_STRAP3 */
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PAD_NC(GPP_H2, DN_20K),
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/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H3, 1, DEEP),
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/* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */
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PAD_CFG_GPO(GPP_H10, 1, DEEP),
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/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
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/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */
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PAD_CFG_GPI(GPP_H19, NONE, DEEP),
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/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
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/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
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/* R5 : HDA_SDI1 ==> HP_INT_L */
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PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH),
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/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
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/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
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/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
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/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
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/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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/* GPD6: SLP_A# ==> NC */
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PAD_NC(GPD6, NONE),
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/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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};
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const struct pad_config *variant_base_gpio_table(size_t *num)
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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@ -25,12 +227,3 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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static const struct cros_gpio cros_gpios[] = {
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};
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const struct cros_gpio *variant_cros_gpios(size_t *num)
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{
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*num = ARRAY_SIZE(cros_gpios);
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return cros_gpios;
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}
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@ -5,6 +5,8 @@
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#include <baseboard/gpio.h>
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/* Copied from baseboard and may need to change for the new variant. */
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#undef GPIO_EC_IN_RW
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/* EC in RW */
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#define GPIO_EC_IN_RW GPP_F17
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#endif
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@ -4,7 +4,53 @@ chip soc/intel/tigerlake
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# Enable Command Mirroring for controller 0 channel 0 and 1,
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# and controller 1 channel 0 and 1.
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register "CmdMirror" = "0x00000033"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
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register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
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device domain 0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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register "uid" = "0"
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register "desc" = ""Right Speaker Amp""
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register "name" = ""MAXR""
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device i2c 31 on
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "2"
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register "imon_slot_no" = "3"
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register "uid" = "1"
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register "desc" = ""Left Speaker Amp""
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register "name" = ""MAXL""
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device i2c 32 on
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end
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end
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end # I2C #0 0xA0E8
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device pci 15.1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""GDIX0000""
|
||||
|
|
|
|||
Loading…
Reference in New Issue