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soc/intel/tigerlake: Include few more Tigerlake device IDs 

This patch performs below operations
1. Add few more MCH, ESPI and IGD IDs
2. Remove TGL-H IDs
3. Rename existing as per applicable names
4. Remove TODO from report_platform.c file
5. Include TGL IDs into report_platform.c file

Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Subrata Banik 2019-11-12 12:47:43 +05:30 committed by Patrick Georgi
parent 10c8ad8d78
commit ae695757f4
5 changed files with 138 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
src/include/device/pci_ids.h
View File

@ -2767,7 +2767,38 @@
#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284
#define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285
#define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286
#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080
#define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081
#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082
#define PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI 0xA083
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_1 0xA084
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_2 0xA085
#define PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI 0xA086
#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI 0xA087
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_3 0xA088
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_4 0xA089
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_5 0xA08A
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_6 0xA08B
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_7 0xA08C
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_8 0xA08D
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_9 0xA08E
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_10 0xA08F
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_11 0xA090
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_12 0xA091
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_13 0xA092
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_14 0xA093
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_15 0xA094
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_16 0xA095
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_17 0xA096
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_18 0xA097
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_19 0xA098
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_20 0xA099
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_21 0xA09A
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_22 0xA09B
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_23 0xA09C
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@ -3229,10 +3260,10 @@
#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60
#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49
#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20
#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40
#define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49
#define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@ -3284,7 +3315,8 @@
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23

8
src/soc/intel/common/block/graphics/graphics.c
View File

@ -207,10 +207,10 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CML_GT1_H_2,
PCI_DEVICE_ID_INTEL_CML_GT2_H_1,
PCI_DEVICE_ID_INTEL_CML_GT2_H_2,
PCI_DEVICE_ID_INTEL_TGL_GT1,
PCI_DEVICE_ID_INTEL_TGL_GT2_UY,
PCI_DEVICE_ID_INTEL_TGL_GT2,
PCI_DEVICE_ID_INTEL_TGL_GT2_Y,
PCI_DEVICE_ID_INTEL_TGL_GT0,
PCI_DEVICE_ID_INTEL_TGL_GT2_ULT,
PCI_DEVICE_ID_INTEL_TGL_GT2_ULX,
PCI_DEVICE_ID_INTEL_TGL_GT3_ULT,
0,
};

33
src/soc/intel/common/block/lpc/lpc.c
View File

@ -190,7 +190,38 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC,
PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC,
PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC,
PCI_DEVICE_ID_INTEL_TGL_ESPI,
PCI_DEVICE_ID_INTEL_TGP_ESPI_0,
PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI,
PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI,
PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI,
PCI_DEVICE_ID_INTEL_TGP_ESPI_1,
PCI_DEVICE_ID_INTEL_TGP_ESPI_2,
PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI,
PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI,
PCI_DEVICE_ID_INTEL_TGP_ESPI_3,
PCI_DEVICE_ID_INTEL_TGP_ESPI_4,
PCI_DEVICE_ID_INTEL_TGP_ESPI_5,
PCI_DEVICE_ID_INTEL_TGP_ESPI_6,
PCI_DEVICE_ID_INTEL_TGP_ESPI_7,
PCI_DEVICE_ID_INTEL_TGP_ESPI_8,
PCI_DEVICE_ID_INTEL_TGP_ESPI_9,
PCI_DEVICE_ID_INTEL_TGP_ESPI_10,
PCI_DEVICE_ID_INTEL_TGP_ESPI_11,
PCI_DEVICE_ID_INTEL_TGP_ESPI_12,
PCI_DEVICE_ID_INTEL_TGP_ESPI_13,
PCI_DEVICE_ID_INTEL_TGP_ESPI_14,
PCI_DEVICE_ID_INTEL_TGP_ESPI_15,
PCI_DEVICE_ID_INTEL_TGP_ESPI_16,
PCI_DEVICE_ID_INTEL_TGP_ESPI_17,
PCI_DEVICE_ID_INTEL_TGP_ESPI_18,
PCI_DEVICE_ID_INTEL_TGP_ESPI_19,
PCI_DEVICE_ID_INTEL_TGP_ESPI_20,
PCI_DEVICE_ID_INTEL_TGP_ESPI_21,
PCI_DEVICE_ID_INTEL_TGP_ESPI_22,
PCI_DEVICE_ID_INTEL_TGP_ESPI_23,
PCI_DEVICE_ID_INTEL_TGP_ESPI_24,
PCI_DEVICE_ID_INTEL_TGP_ESPI_25,
PCI_DEVICE_ID_INTEL_TGP_ESPI_26,
0
};

1
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -363,6 +363,7 @@ static const unsigned short systemagent_ids[] = {
PCI_DEVICE_ID_INTEL_CML_H,
PCI_DEVICE_ID_INTEL_CML_H_8_2,
PCI_DEVICE_ID_INTEL_TGL_ID_U,
PCI_DEVICE_ID_INTEL_TGL_ID_U_1,
PCI_DEVICE_ID_INTEL_TGL_ID_Y,
0
};

66
src/soc/intel/tigerlake/bootblock/report_platform.c
View File

@ -33,9 +33,69 @@
#define BIOS_SIGN_ID 0x8B
/*
* TODO: Add TGL specific CPU/SA/PCH IDs here
*/
static struct {
u32 cpuid;
const char *name;
} cpu_table[] = {
{ CPUID_TIGERLAKE_A0, "Tigerlake A0" },
};
static struct {
u16 mchid;
const char *name;
} mch_table[] = {
{ PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" },
{ PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
{ PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
};
static struct {
u16 espiid;
const char *name;
} pch_table[] = {
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" },
{ PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
};
static struct {
u16 igdid;
const char *name;
} igd_table[] = {
{ PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" },
{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },
{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
{ PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
};
static inline uint8_t get_dev_revision(pci_devfn_t dev)
{