mb/asrock/g41m_vs3_r2: Add mainboard
The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Felix Held
parent
8165583ed9
commit
ae7bd1eb23
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@ -14,7 +14,8 @@
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# GNU General Public License for more details.
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#
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if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS
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if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS \
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|| BOARD_ASROCK_G41M_VS3_R2_0
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -24,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
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select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \
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|| BOARD_ASROCK_G41M_GS
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|| BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select PCIEXP_ASPM
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@ -46,18 +47,21 @@ config VARIANT_DIR
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default "g41c-gs-r2" if BOARD_ASROCK_G41C_GS_R2_0
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default "g41c-gs" if BOARD_ASROCK_G41C_GS
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default "g41m-gs" if BOARD_ASROCK_G41M_GS
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default "g41m-vs3-r2" if BOARD_ASROCK_G41M_VS3_R2_0
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config MAINBOARD_PART_NUMBER
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string
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default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
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default "G41C-GS" if BOARD_ASROCK_G41C_GS
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default "G41M-GS" if BOARD_ASROCK_G41M_GS
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default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0
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config DEVICETREE
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string
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default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
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default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
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default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS
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default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0
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config MAX_CPUS
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int
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@ -6,3 +6,6 @@ config BOARD_ASROCK_G41C_GS
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config BOARD_ASROCK_G41M_GS
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bool "G41M-GS"
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config BOARD_ASROCK_G41M_VS3_R2_0
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bool "G41M-VS3 R2.0"
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@ -18,6 +18,44 @@
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* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
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*/
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#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)
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If (PICM) {
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Return (Package() {
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/* PCI1 SLOT 1 */
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Package() { 0x0000ffff, 0, 0, 0x11},
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Package() { 0x0000ffff, 1, 0, 0x12},
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Package() { 0x0000ffff, 2, 0, 0x13},
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Package() { 0x0000ffff, 3, 0, 0x10},
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/* PCI1 SLOT 2 */
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Package() { 0x0002ffff, 0, 0, 0x17},
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Package() { 0x0002ffff, 1, 0, 0x14},
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Package() { 0x0002ffff, 2, 0, 0x15},
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Package() { 0x0002ffff, 3, 0, 0x16},
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/* device not in lspci but in vendor DSDT */
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/* Package() { 0x0008ffff, 0, 0, 0x14}, */
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})
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} Else {
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Return (Package() {
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
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Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
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Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
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Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
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Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
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/* device not in lspci but in vendor DSDT */
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/* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */
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})
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}
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#else
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/* IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) \
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|| IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) \
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|| IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) */
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If (PICM) {
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Return (Package() {
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/* PCI1 SLOT 1 */
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@ -51,3 +89,4 @@ If (PICM) {
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/* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */
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})
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}
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#endif
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@ -0,0 +1,139 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
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end
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end
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device domain 0 on # PCI domain
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subsystemid 0x1458 0x5000 inherit
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device pci 0.0 on # Host Bridge
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subsystemid 0x1849 0x2e30
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end
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device pci 1.0 on end # PEG
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device pci 2.0 on # Integrated graphics controller
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subsystemid 0x1849 0x2e32
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end
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device pci 3.0 off end # ME
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device pci 3.1 off end # ME
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chip southbridge/intel/i82801gx # Southbridge
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x0b"
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x440"
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device pci 1b.0 on # Audio
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subsystemid 0x1849 0x3662
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end
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device pci 1c.0 on end # PCIe 1
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device pci 1c.1 on end # PCIe 2 (ethernet)
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1c.4 off end # PCIe 5
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device pci 1c.5 off end # PCIe 6
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device pci 1d.0 on # USB
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subsystemid 0x1849 0x27c8
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end
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device pci 1d.1 on # USB
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subsystemid 0x1849 0x27c9
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end
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device pci 1d.2 on # USB
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subsystemid 0x1849 0x27ca
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end
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device pci 1d.3 on # USB
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subsystemid 0x1849 0x27cb
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end
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device pci 1d.7 on # USB
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subsystemid 0x1849 0x27cc
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end
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device pci 1e.0 on end # PCI bridge
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device pci 1e.2 off end # AC'97 Audio
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device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # ISA bridge
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subsystemid 0x1849 0x27b8
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chip superio/winbond/w83627dhg
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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# global
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irq 0x28 = 0x70
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irq 0x2c = 0xd2
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# parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM2
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device pnp 2e.5 on # Keyboard & MOUSE
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 0x0C
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end
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device pnp 2e.6 off end # SPI
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device pnp 2e.7 off end # GPIO6
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device pnp 2e.8 off end # WDT0#, PLED
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device pnp 2e.9 on end # GPIO2
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device pnp 2e.109 off end # GPIO3
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device pnp 2e.209 on # GPIO4
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irq 0xf4 = 0xb3
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end
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device pnp 2e.309 off end # GPIO5
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # Power dram during s3
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end
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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device pnp 2e.c off end # PECI, SST
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end
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end
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device pci 1f.1 on # PATA/IDE
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subsystemid 0x1849 0x27df
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end
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device pci 1f.2 on # SATA
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subsystemid 0x1849 0x27c0
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end
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device pci 1f.3 on # SMbus
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subsystemid 0x1849 0x27da
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chip drivers/i2c/ck505 # W83115RG-965
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# set SATA to fixed 100Mhz refclk
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register "mask" = "{ 0x02 }"
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register "regs" = "{ 0x02 }"
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device i2c 69 on end
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end
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end
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end
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end
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end
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@ -0,0 +1,118 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_GPIO,
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.gpio10 = GPIO_MODE_GPIO,
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.gpio12 = GPIO_MODE_GPIO,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_GPIO,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_GPIO,
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.gpio20 = GPIO_MODE_GPIO,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_GPIO,
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.gpio26 = GPIO_MODE_GPIO,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio9 = GPIO_DIR_OUTPUT,
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.gpio10 = GPIO_DIR_OUTPUT,
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.gpio12 = GPIO_DIR_INPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_OUTPUT,
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.gpio18 = GPIO_DIR_OUTPUT,
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.gpio20 = GPIO_DIR_OUTPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio25 = GPIO_DIR_OUTPUT,
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.gpio26 = GPIO_DIR_INPUT,
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.gpio27 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_LOW,
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.gpio9 = GPIO_LEVEL_LOW,
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.gpio10 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio16 = GPIO_LEVEL_HIGH,
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.gpio18 = GPIO_LEVEL_HIGH,
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.gpio20 = GPIO_LEVEL_LOW,
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.gpio24 = GPIO_LEVEL_HIGH,
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.gpio25 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio0 = GPIO_INVERT,
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.gpio6 = GPIO_INVERT,
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.gpio12 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_OUTPUT,
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.gpio33 = GPIO_DIR_OUTPUT,
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.gpio34 = GPIO_DIR_INPUT,
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.gpio38 = GPIO_DIR_INPUT,
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.gpio39 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio32 = GPIO_LEVEL_HIGH,
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.gpio33 = GPIO_LEVEL_HIGH,
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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};
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Loading…
Reference in New Issue