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mainboard/intel/cannonlake_rvp: enable SATA 

Set sata enable FSP parameters.

Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2017-09-05 10:58:07 -07:00 committed by Martin Roth
parent e2592be952
commit ae7e7ccdc9
2 changed files with 8 additions and 0 deletions
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4
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -28,6 +28,10 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "SataEnable" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device

4
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -28,6 +28,10 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "SataEnable" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device