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mb/google/brya/var/anahera: Enable SaGv 

Enable SaGv support for anahera/anahera4es.

BUG=b:211362081
TEST=FW_NAME=anahera emerge-brya coreboot

Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2021-12-20 13:55:57 +06:00 committed by Felix Held
parent 591789b50b
commit ae8004ad5f
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/google/brya/variants/anahera/overridetree.cb
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@ -33,6 +33,7 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0" register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |

1
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -33,6 +33,7 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0" register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |