- Compile fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
50086df616
commit
ae948f78e6
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@ -1,19 +1,6 @@
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#ifndef ASM_H
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#define ASM_H
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#define ASSEMBLER
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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*/
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#define I386_ALIGN_TEXT 0
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#define I386_ALIGN_DATA 0
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#define STATIC(x) .align I386_ALIGN_TEXT; EXT(x):
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#define GLOBAL(x) .globl EXT(x); STATIC(x)
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#define ENTRY(x) .text; GLOBAL(x)
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#define ASSEMBLER 1
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#endif /* ASM_H */
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@ -29,19 +29,6 @@ it with the version available from LANL.
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*
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*/
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/*
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* Config registers.
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*/
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/* yeah, yeah, I know these are macros, which is bad. Don't forget:
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* we have almost no assembly, so I am not worrying just yet about this.
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* we'll fix it someday if we care. My guess is we won't.
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*/
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/* well we want functions. But first we want to see it work at all. */
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#undef FUNCTIONS
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#ifndef FUNCTIONS
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#define RET_LABEL(label) \
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jmp label##_done
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@ -58,310 +45,10 @@ label##_done:
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jmp *%esp
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#define DELAY(x) mov x, %ecx ;\
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1: loop 1b ;\
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/*
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* Macro: PCI_WRITE_CONFIG_BYTE
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* Arguments: %eax address to write to (includes bus, device, function, &offset)
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* %dl byte to write
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*
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* Results: none
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*
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* Trashed: %eax, %edx
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* Effects: writes a single byte to pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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* And the tricks it does cannot scale beyond writing a single byte.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the data byte
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* in the high half of edx.
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*
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* In %edx[3] it stores the byte to write.
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_WRITE_CONFIG_BYTE \
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shll $8, %edx ; \
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movb %al, %dl ; \
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andb $0x3, %dl ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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movb %dh, %al ; \
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movb $0, %dh ; \
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addl $0xcfc, %edx ; \
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outb %al, %dx
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/*
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* Macro: PCI_WRITE_CONFIG_WORD
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* Arguments: %eax address to write to (includes bus, device, function, &offset)
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* %ecx word to write
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*
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* Results: none
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*
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* Trashed: %eax, %edx
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* Preserved: %ecx
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* Effects: writes a single byte to pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the least significant
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* bits of the address in the high half of edx.
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*
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_WRITE_CONFIG_WORD \
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movb %al, %dl ; \
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andl $0x3, %edx ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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movl %ecx, %eax ; \
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addl $0xcfc, %edx ; \
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outw %ax, %dx
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/*
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* Macro: PCI_WRITE_CONFIG_DWORD
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* Arguments: %eax address to write to (includes bus, device, function, &offset)
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* %ecx dword to write
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*
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* Results: none
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*
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* Trashed: %eax, %edx
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* Preserved: %ecx
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* Effects: writes a single byte to pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the least significant
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* bits of the address in the high half of edx.
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*
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_WRITE_CONFIG_DWORD \
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movb %al, %dl ; \
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andl $0x3, %edx ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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movl %ecx, %eax ; \
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addl $0xcfc, %edx ; \
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outl %eax, %dx
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/*
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* Macro: PCI_READ_CONFIG_BYTE
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* Arguments: %eax address to read from (includes bus, device, function, &offset)
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*
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* Results: %al Byte read
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*
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* Trashed: %eax, %edx
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* Effects: reads a single byte from pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the least significant
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* bits of the address in the high half of edx.
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*
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_READ_CONFIG_BYTE \
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movb %al, %dl ; \
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andl $0x3, %edx ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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addl $0xcfc, %edx ; \
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inb %dx, %al
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/*
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* Macro: PCI_READ_CONFIG_WORD
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* Arguments: %eax address to read from (includes bus, device, function, &offset)
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*
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* Results: %ax word read
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*
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* Trashed: %eax, %edx
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* Effects: reads a 2 bytes from pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the least significant
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* bits of the address in the high half of edx.
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*
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_READ_CONFIG_WORD \
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movb %al, %dl ; \
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andl $0x3, %edx ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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addl $0xcfc, %edx ; \
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inw %dx, %ax
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/*
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* Macro: PCI_READ_CONFIG_DWORD
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* Arguments: %eax address to read from (includes bus, device, function, &offset)
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*
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* Results: %eax
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*
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* Trashed: %edx
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* Effects: reads 4 bytes from pci config space
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*
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* Notes: This routine is optimized for minimal register usage.
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*
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* What it does is almost simple.
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* It preserves %eax (baring special bits) until it is written
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* out to the appropriate port. And hides the least significant
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* bits of the address in the high half of edx.
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*
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* In %edx[2] it stores the lower three bits of the address.
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*/
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#define PCI_READ_CONFIG_DWORD \
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movb %al, %dl ; \
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andl $0x3, %edx ; \
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shll $16, %edx ; \
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\
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orl $0x80000000, %eax ; \
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andl $0xfffffffc, %eax ; \
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movw $0xcf8, %dx ; \
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outl %eax, %dx ; \
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\
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shrl $16, %edx ; \
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addl $0xcfc, %edx ; \
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inl %dx, %eax
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#define CS_READ(which) \
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mov $0x80000000,%eax ; \
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mov which,%ax ; \
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and $0xfc,%al /* clear bits 1-0 */ ; \
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mov $0xcf8,%dx /* port 0xcf8 ?*/ ; \
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outl %eax,%dx /* open up CS config */ ; \
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add $0x4,%dl /* 0xcfc data port 0 */ ; \
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mov which,%al ; \
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and $0x3,%al /* only bits 1-0 */ ; \
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add %al,%dl ; \
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inb %dx,%al /* read */ ; \
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#define CS_WRITE(which, data) \
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mov $0x80000000,%eax /* 32bit word with bit 31 set */ ; \
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mov which,%ax /* put the reg# in the low part */ ; \
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and $0xfc,%al /* dword align the reg# */ ; \
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mov $0xcf8,%dx /* enable port */ ; \
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outl %eax,%dx ; \
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add $0x4,%dl /* 1st data port */ ; \
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mov which,%ax /* register# */ ; \
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and $0x3,%ax ; \
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add %al,%dl ; \
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mov data, %al ; \
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outb %al,%dx /* write to reg */
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#define REGBIS(which, bis) \
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CS_READ(which) ;\
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movb bis, %cl ;\
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orb %al, %cl ;\
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CS_WRITE(which, %cl)
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#define REGBIC(which, bic) \
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CS_READ(which) ;\
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movb bic, %cl ;\
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notb %cl ;\
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andb %al, %cl ;\
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CS_WRITE(which, %cl)
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/* macro to BIC and BIS a reg. calls read a reg,
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* does a BIC and then a BIS on it.
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* to clear no bits, make BIC 0.
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* to set no bits, make BIS 0
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*/
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#define REGBICBIS(which, bic, bis) \
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CS_READ(which) ;\
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movb bic, %cl ;\
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notb %cl ;\
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andb %cl, %al ;\
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movb bis, %cl ;\
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orb %al, %cl ;\
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CS_WRITE(which, %cl)
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#else
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NO FUNCTIONS YET!
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#endif
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/* originally this macro was from STPC BIOS */
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#define intel_chip_post_macro(value) \
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movb $value, %al ; \
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outb %al, $0x80
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#define INTEL_PDATA_MAGIC 0xdeadbeef
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/* SLOW_DOWN_IO is a delay we can use that is roughly cpu neutral,
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* and can be used before memory or timer chips come up.
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* Since this hits the isa bus it's roughly
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*/
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#define SLOW_DOWN_IO inb $0x80, %al
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#endif /* ROM_INTEL_H */
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@ -20,16 +20,16 @@ _start:
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intel_chip_post_macro(0x13) /* post 12 */
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/** clear stack */
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leal EXT(_stack), %edi
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movl $EXT(_estack), %ecx
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leal _stack, %edi
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movl $_estack, %ecx
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subl %edi, %ecx
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xorl %eax, %eax
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rep
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stosb
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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leal _bss, %edi
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movl $_ebss, %ecx
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subl %edi, %ecx
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jz .Lnobss
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xorl %eax, %eax
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@ -50,7 +50,7 @@ _start:
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1: addl $4, %ebx
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cmpl $(MAX_CPUS << 2), %ebx
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je 2
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cmpl %eax, EXT(initial_apicid)(%ebx)
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cmpl %eax, initial_apicid(%ebx)
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jne 1b
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2: shrl $2, %ebx
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@ -78,7 +78,7 @@ _start:
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movl %ebp, %esp
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/* The boot_complete flag has already been pushed */
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call EXT(hardwaremain)
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call hardwaremain
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/*NOTREACHED*/
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.Lhlt:
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intel_chip_post_macro(0xee) /* post fe */
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@ -28,10 +28,10 @@ it with the version available from LANL.
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/* .section ".rom.text" */
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#include <arch/rom_segs.h>
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.code16
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.globl EXT(_start)
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.type EXT(_start), @function
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.globl _start
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.type _start, @function
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EXT(_start):
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_start:
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cli
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/* thanks to kmliu@sis.tw.com for this TBL fix ... */
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@ -84,7 +84,7 @@ EXT(_start):
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movw %cs, %ax
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shlw $4, %ax
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movw $EXT(gdtptr16_offset), %bx
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movw $gdtptr16_offset, %bx
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subw %ax, %bx
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data32 lgdt %cs:(%bx)
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@ -101,12 +101,12 @@ EXT(_start):
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*/
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.align 4
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.globl EXT(gdtptr16)
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EXT(gdtptr16):
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.globl gdtptr16
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gdtptr16:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.globl EXT(_estart)
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EXT(_estart):
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.globl _estart
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_estart:
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.code32
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@ -6,10 +6,10 @@
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.code32
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.align 4
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.globl EXT(gdtptr)
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.globl gdtptr
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gdt:
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EXT(gdtptr):
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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@ -37,8 +37,8 @@ gdt_end:
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* cache will be reloaded.
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*/
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.align 4
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.globl EXT(protected_start)
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EXT(protected_start):
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.globl protected_start
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protected_start:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_start
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@ -1,10 +1,10 @@
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.section ".reset"
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.code16
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.globl EXT(reset_vector)
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EXT(reset_vector):
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.globl reset_vector
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reset_vector:
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. = 0x8;
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.code32
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jmp EXT(protected_start)
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jmp protected_start
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.previous
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@ -7,6 +7,16 @@
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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static void memreset_setup(const struct mem_controller *ctrl)
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{
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}
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static void memreset(const struct mem_controller *ctrl)
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{
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}
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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