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broadcom: Remove SoC and board support 

The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.

* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries

Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Philipp Deppenwiese 2018-11-28 18:50:11 +01:00
parent 48418757cb
commit aea00f496b
73 changed files with 1 additions and 29729 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/util.md
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@ -18,7 +18,6 @@ Technologies, for example the Pistachio SoC. `C`
`Yacc`
* __board_status__ - Tools to collect logs and upload them to the board
status repository `Bash` `Go`
* __broadcom__ - Generate Broadcom secure boot image. `C`
* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
file `Python`
* __cbfstool__

2
MAINTAINERS
View File

@ -404,12 +404,10 @@ S: Orphaned
F: src/cpu/allwinner/
F: src/cpu/armltd/
F: src/cpu/ti/
F: src/soc/broadcom/
F: src/soc/marvell/
F: src/soc/qualcomm/
F: src/soc/samsung/
F: util/arm_boot_tools/
F: util/broadcom/
F: util/exynos/
F: util/ipqheader/

2
Makefile.inc
View File

@ -93,7 +93,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
subdirs-y += src/superio
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
subdirs-y += src/cpu src/vendorcode
subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
subdirs-y += util/cbfstool util/sconfig util/nvramtool
subdirs-y += util/futility util/marvell util/bincfg
subdirs-y += $(wildcard src/arch/*)
subdirs-y += src/mainboard/$(MAINBOARDDIR)

53
src/mainboard/google/purin/Kconfig
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@ -1,53 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_GOOGLE_PURIN
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_2048
select COMMON_CBFS_SPI_WRAPPER
select MAINBOARD_HAS_CHROMEOS
select SOC_BROADCOM_CYGNUS
select SPI_FLASH
select SPI_FLASH_SPANSION
select SPI_FLASH_STMICRO # required for the reference board BCM958305K
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_VBNV_FLASH
config MAINBOARD_DIR
string
default google/purin
config MAINBOARD_PART_NUMBER
string
default "Purin"
config MAINBOARD_VENDOR
string
default "Google"
config DRAM_SIZE_MB
int
default 256
config GBB_HWID
string
depends on CHROMEOS
default "Purin TEST 1"
endif # BOARD_GOOGLE_PURIN

2
src/mainboard/google/purin/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_GOOGLE_PURIN
bool "Purin"

36
src/mainboard/google/purin/Makefile.inc
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@ -1,36 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
bootblock-y += bootblock.c
bootblock-y += boardid.c
bootblock-y += chromeos.c
bootblock-y += reset.c
verstage-y += boardid.c
verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += boardid.c
romstage-y += chromeos.c
romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

6
src/mainboard/google/purin/board_info.txt
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@ -1,6 +0,0 @@
Vendor name: Google
Board name: Purin Broadcom Cygnus reference board
Category: eval
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

21
src/mainboard/google/purin/boardid.c
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@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boardid.h>
uint32_t board_id(void)
{
return -1;
}

20
src/mainboard/google/purin/bootblock.c
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@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 20145Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
void bootblock_mainboard_init(void)
{
}

31
src/mainboard/google/purin/chromeos.c
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@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
}
int get_recovery_mode_switch(void)
{
return 0;
}
int get_write_protect_state(void)
{
return 0;
}

32
src/mainboard/google/purin/chromeos.fmd
View File

@ -1,32 +0,0 @@
FLASH@0x0 0x200000 {
WP_RO@0x0 0x100000 {
RO_SECTION@0x0 0xf0000 {
BOOTBLOCK@0 128K
COREBOOT(CBFS)@0x20000 0x60000
FMAP@0x80000 0x1000
GBB@0x81000 0x6ef00
RO_FRID@0xeff00 0x100
}
RO_VPD@0xf0000 0x10000
}
RW_SECTION_A@0x100000 0x58000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x55f00
RW_FWID_A@0x57f00 0x100
}
RW_SHARED@0x158000 0x4000 {
SHARED_DATA@0x0 0x4000
}
RW_ELOG@0x15c000 0x4000
RW_GPT@0x160000 0x20000 {
RW_GPT_PRIMARY@0x0 0x10000
RW_GPT_SECONDARY@0x10000 0x10000
}
RW_SECTION_B@0x180000 0x58000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x55f00
RW_FWID_B@0x57f00 0x100
}
RW_VPD@0x1d8000 0x8000
RW_NVRAM@0x1e0000 0x10000
}

19
src/mainboard/google/purin/devicetree.cb
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@ -1,19 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# TODO fill with Versatile Express board data in QEMU.
chip soc/broadcom/cygnus
device cpu_cluster 0 on end
end

42
src/mainboard/google/purin/mainboard.c
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@ -1,42 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <boot/coreboot_tables.h>
#include <symbols.h>
static void mainboard_init(struct device *dev)
{
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

14
src/mainboard/google/purin/memlayout.ld
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@ -1,14 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/memlayout.ld>

20
src/mainboard/google/purin/reset.c
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@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <reset.h>
void do_board_reset(void)
{
}

2
src/soc/broadcom/Kconfig
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@ -1,2 +0,0 @@
# Load all chipsets
source "src/soc/broadcom/*/Kconfig"

81
src/soc/broadcom/cygnus/Kconfig
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@ -1,81 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOC_BROADCOM_CYGNUS
bool
default n
select ARCH_BOOTBLOCK_ARMV7
select ARCH_RAMSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_VERSTAGE_ARMV7
select BOOTBLOCK_CONSOLE
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
if SOC_BROADCOM_CYGNUS
config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_RETURN_FROM_VERSTAGE
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0x18023000
config CYGNUS_DDR333
def_bool n
config CYGNUS_DDR400
def_bool n
config CYGNUS_DDR533
def_bool n
config CYGNUS_DDR667
def_bool n
config CYGNUS_DDR800
bool "DDR Speed at 800MHz"
default y
config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
bool "Enable DDR auto self-refresh"
default y
help
Warning: M0 expects that auto self-refresh is enabled. Modify
with caution.
config CYGNUS_SHMOO_REUSE_DDR_32BIT
bool "Indicate if DDR width is 32-bit"
default n
config CYGNUS_SDRAM_TEST_DDR
bool "Run a write-read test on DDR after initialization"
default n
config CYGNUS_PRINT_SHMOO_DEBUG
bool "Print debug info for shmoo"
default n
config CYGNUS_GPIO_TEST
bool "Run a test on gpio"
default n
endif

100
src/soc/broadcom/cygnus/Makefile.inc
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@ -1,100 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y)
bootblock-y += bootblock.c
bootblock-y += cbmem.c
bootblock-y += i2c.c
bootblock-y += timer.c
bootblock-y += tz.c
bootblock-y += hw_init.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-y += ns16550.c
endif
verstage-y += i2c.c
verstage-y += timer.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
verstage-y += ns16550.c
romstage-y += cbmem.c
romstage-y += i2c.c
romstage-y += timer.c
romstage-y += romstage.c
romstage-y += sdram.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += ns16550.c
romstage-y += ddr_init.c
romstage-y += ddr_init_table.c
romstage-y += shmoo_and28.c
romstage-y += phy_reg_access.c
romstage-y += ydc_ddr_bist.c
romstage-y += timer.c
romstage-y += gpio.c
romstage-y += iomux.c
ramstage-y += cbmem.c
ramstage-y += i2c.c
ramstage-y += sdram.c
ramstage-y += soc.c
ramstage-y += timer.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += ns16550.c
ramstage-y += usb.c
CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
ifneq ($(V),1)
redirect := > /dev/null
endif
# Options used in the command line:
# -out: path of the output file
# -config: path to the file containing unauth header
# -hmac: path to the file containing hmac for sha256
# -bl: boot image file, ie. input file
#
# Authenticated header parameters:
#
# SBIConfiguration /* Indicates SBI config */
# SYMMETRIC 0x0040
#
# CustomerID; /* Customer ID */
# TYPE bits [31-28]
# PRODUCTION 0x6
# DEVELOPMENT 0x9
# CUSTOMER_ID bits [27-0]
#
# ProductID; /* Product ID */
#
# CustomerRevisionID; /* Customer Revision ID */
#
# SBIUsage /* Boot Image Usage */
# NONE 0 /* All purposes */
# SLEEP 1
# DEEP_SLEEP 2
# EXCEPTION 4
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
$(objutil)/broadcom/secimage/secimage \
util/broadcom/unauth.cfg \
util/broadcom/khmacsha256
@printf " SIGN $(subst $(obj)/,,$(@))\n"
$(objutil)/broadcom/secimage/secimage -out $@ \
-config util/broadcom/unauth.cfg \
-hmac util/broadcom/khmacsha256 -bl $<
endif

35
src/soc/broadcom/cygnus/bootblock.c
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@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cache.h>
#include <bootblock_common.h>
#include <stddef.h>
#include <symbols.h>
#include <soc/hw_init.h>
void bootblock_soc_init(void)
{
/*
* not only for speed but for preventing the CPU from crashing.
* the CPU is not happy when cache is cleaned without mmu turned on.
*/
mmu_init();
mmu_config_range(0, 4096, DCACHE_OFF);
mmu_config_range_kb((uintptr_t)_sram/KiB, _sram_size/KiB,
DCACHE_WRITETHROUGH);
dcache_mmu_enable();
hw_init();
}

24
src/soc/broadcom/cygnus/cbmem.c
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@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stddef.h>
#include <symbols.h>
#include <soc/sdram.h>
void *cbmem_top(void)
{
return _dram + sdram_size_mb()*MiB;
}

1672
src/soc/broadcom/cygnus/ddr_init.c
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File diff suppressed because it is too large Load Diff

1810
src/soc/broadcom/cygnus/ddr_init_table.c
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File diff suppressed because it is too large Load Diff

501
src/soc/broadcom/cygnus/gpio.c
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@ -1,501 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <gpio.h>
#include <stdlib.h>
#include <delay.h>
#define dev_dbg(chip, fmt, args...) printk(BIOS_DEBUG, "[%s] " fmt, \
chip->label, args)
#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c
#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c
#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24
#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34
#define CYGNUS_GPIO_RES_EN_OFFSET 0x38
/* drive strength control for ASIU GPIO */
#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
/* drive strength control for CCM/CRMU (AON) GPIO */
#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00
#define GPIO_BANK_SIZE 0x200
#define NGPIOS_PER_BANK 32
#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
#define GPIO_DRV_STRENGTH_BITS 3
#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
/*
* Cygnus GPIO core
*
* @base: I/O register base for Cygnus GPIO controller
* @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
* has the PINCONF support implemented outside of the GPIO block
* @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
* @pinmux_is_supported: flag to indicate this GPIO controller contains pins
* that can be individually muxed to GPIO
* @pctl_priv: pointer to pinctrl handle
*/
struct cygnus_gpio {
void *base;
void *io_ctrl;
const char *label;
int gpio_base;
u16 ngpio;
unsigned num_banks;
int pinmux_is_supported;
void *pctl_priv;
};
/*
* GPIO cores table
*
* Cygnus has 3 gpio cores. The tables contains descriptors of those cores.
*/
struct cygnus_gpio cygnus_gpio_table[] = {
{
.base = (void *)0x03024800,
.io_ctrl = (void *)0x03024008,
.label = "gpio_crmu",
.gpio_base = 170,
.ngpio = 6,
},
{
.base = (void *)0x1800a000,
.io_ctrl = (void *)0x0301d164,
.label = "gpio_ccm",
.gpio_base = 0,
.ngpio = 24,
},
{
.base = (void *)0x180a5000,
.label = "gpio_asiu",
.gpio_base = 24,
.ngpio = 146,
.pinmux_is_supported = 1
}
};
/*
* Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
* pinctrl pin space
*/
struct cygnus_gpio_pin_range {
unsigned offset;
unsigned pin_base;
unsigned num_pins;
};
#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
/*
* Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins.
* This is for ASIU gpio. The offset is based on ASIU gpios.
*/
static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
CYGNUS_PINRANGE(0, 42, 1),
CYGNUS_PINRANGE(1, 44, 3),
CYGNUS_PINRANGE(4, 48, 1),
CYGNUS_PINRANGE(5, 50, 3),
CYGNUS_PINRANGE(8, 126, 1),
CYGNUS_PINRANGE(9, 155, 1),
CYGNUS_PINRANGE(10, 152, 1),
CYGNUS_PINRANGE(11, 154, 1),
CYGNUS_PINRANGE(12, 153, 1),
CYGNUS_PINRANGE(13, 127, 3),
CYGNUS_PINRANGE(16, 140, 1),
CYGNUS_PINRANGE(17, 145, 7),
CYGNUS_PINRANGE(24, 130, 10),
CYGNUS_PINRANGE(34, 141, 4),
CYGNUS_PINRANGE(38, 54, 1),
CYGNUS_PINRANGE(39, 56, 3),
CYGNUS_PINRANGE(42, 60, 3),
CYGNUS_PINRANGE(45, 64, 3),
CYGNUS_PINRANGE(48, 68, 2),
CYGNUS_PINRANGE(50, 84, 6),
CYGNUS_PINRANGE(56, 94, 6),
CYGNUS_PINRANGE(62, 72, 1),
CYGNUS_PINRANGE(63, 70, 1),
CYGNUS_PINRANGE(64, 80, 1),
CYGNUS_PINRANGE(65, 74, 3),
CYGNUS_PINRANGE(68, 78, 1),
CYGNUS_PINRANGE(69, 82, 1),
CYGNUS_PINRANGE(70, 156, 17),
CYGNUS_PINRANGE(87, 104, 12),
CYGNUS_PINRANGE(99, 102, 2),
CYGNUS_PINRANGE(101, 90, 4),
CYGNUS_PINRANGE(105, 116, 10),
CYGNUS_PINRANGE(123, 11, 1),
CYGNUS_PINRANGE(124, 38, 4),
CYGNUS_PINRANGE(128, 43, 1),
CYGNUS_PINRANGE(129, 47, 1),
CYGNUS_PINRANGE(130, 49, 1),
CYGNUS_PINRANGE(131, 53, 1),
CYGNUS_PINRANGE(132, 55, 1),
CYGNUS_PINRANGE(133, 59, 1),
CYGNUS_PINRANGE(134, 63, 1),
CYGNUS_PINRANGE(135, 67, 1),
CYGNUS_PINRANGE(136, 71, 1),
CYGNUS_PINRANGE(137, 73, 1),
CYGNUS_PINRANGE(138, 77, 1),
CYGNUS_PINRANGE(139, 79, 1),
CYGNUS_PINRANGE(140, 81, 1),
CYGNUS_PINRANGE(141, 83, 1),
CYGNUS_PINRANGE(142, 10, 1)
};
static unsigned cygnus_gpio_to_pin(unsigned gpio)
{
int i;
for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
const struct cygnus_gpio_pin_range *range = cygnus_gpio_pintable
+ i;
if ((gpio < range->offset) ||
(gpio >= (range->offset + range->num_pins)))
continue;
return range->pin_base + (gpio - range->offset);
}
return -1;
}
static struct cygnus_gpio *cygnus_get_gpio_core(unsigned gpio,
unsigned *gpio_offset)
{
int i;
for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
struct cygnus_gpio *chip = cygnus_gpio_table + i;
if ((gpio < chip->gpio_base) ||
(gpio >= (chip->gpio_base + chip->ngpio)))
continue;
*gpio_offset = gpio - chip->gpio_base;
return chip;
}
return NULL;
}
static u32 cygnus_readl(struct cygnus_gpio *chip, unsigned int offset)
{
return read32(chip->base + offset);
}
static void cygnus_writel(struct cygnus_gpio *chip, unsigned int offset,
u32 val)
{
write32(chip->base + offset, val);
}
/**
* cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Cygnus GPIO register
*
* @cygnus_gpio: Cygnus GPIO device
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear. 1 - set; 0 -clear
*/
static void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
unsigned gpio, int set)
{
unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
u32 val;
val = cygnus_readl(chip, offset);
if (set)
val |= BIT(shift);
else
val &= ~BIT(shift);
cygnus_writel(chip, offset, val);
}
static int cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
unsigned gpio)
{
unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
u32 val;
val = cygnus_readl(chip, offset) & BIT(shift);
if (val)
return 1;
else
return 0;
}
/*
* Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
*/
static int cygnus_gpio_request(struct cygnus_gpio *chip, unsigned offset)
{
/* not all Cygnus GPIO pins can be muxed individually */
if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
return 0;
return cygnus_gpio_request_enable(chip->pctl_priv,
cygnus_gpio_to_pin(offset));
}
static void cygnus_gpio_free(struct cygnus_gpio *chip, unsigned offset)
{
if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
return;
cygnus_gpio_disable_free(chip->pctl_priv, cygnus_gpio_to_pin(offset));
}
static int cygnus_gpio_direction_input(struct cygnus_gpio *chip, unsigned gpio)
{
cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 0);
dev_dbg(chip, "gpio:%u set input\n", gpio);
return 0;
}
static int cygnus_gpio_direction_output(struct cygnus_gpio *chip, unsigned gpio,
int value)
{
cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 1);
cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
dev_dbg(chip, "gpio:%u set output, value:%d\n", gpio, value);
return 0;
}
static void cygnus_gpio_set(struct cygnus_gpio *chip, unsigned gpio, int value)
{
cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
dev_dbg(chip, "gpio:%u set, value:%d\n", gpio, value);
}
static int cygnus_gpio_get(struct cygnus_gpio *chip, unsigned gpio)
{
return cygnus_get_bit(chip, CYGNUS_GPIO_DATA_IN_OFFSET, gpio);
}
static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
int disable, int pull_up)
{
if (disable) {
cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 0);
} else {
cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, pull_up);
cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 1);
}
dev_dbg(chip, "gpio:%u set pullup:%d\n", gpio, pull_up);
return 0;
}
#define CYGNUS_GPIO_TEST_AON_GPIO0 170
#define CYGNUS_GPIO_TEST_SPI2_MISO 69
#define CYGNUS_GPIO_TEST_DELAY_S 3
static void cygnus_gpio_test(void)
{
gpio_t gpio_in;
gpio_t gpio_out;
unsigned val;
printk(BIOS_INFO, "Start gpio test...\n");
gpio_in = CYGNUS_GPIO_TEST_AON_GPIO0; /* AON_GPIO0 */
gpio_input(gpio_in);
gpio_input_pulldown(gpio_in);
printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
gpio_in = CYGNUS_GPIO_TEST_SPI2_MISO; /* SPI2_MISO */
gpio_input(gpio_in);
gpio_input_pullup(gpio_in);
printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
val = 0;
gpio_out = CYGNUS_GPIO_TEST_SPI2_MISO;
gpio_output(gpio_out, val);
printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
delay(CYGNUS_GPIO_TEST_DELAY_S);
val = 1;
gpio_set(gpio_out, val);
printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
delay(CYGNUS_GPIO_TEST_DELAY_S);
val = 0;
gpio_set(gpio_out, val);
printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
delay(CYGNUS_GPIO_TEST_DELAY_S);
val = 1;
gpio_set(gpio_out, val);
printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
delay(CYGNUS_GPIO_TEST_DELAY_S);
val = 0;
gpio_set(gpio_out, val);
printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
delay(CYGNUS_GPIO_TEST_DELAY_S);
gpio_free(CYGNUS_GPIO_TEST_AON_GPIO0);
gpio_free(CYGNUS_GPIO_TEST_SPI2_MISO);
printk(BIOS_INFO, "Gpio test completed...\n");
}
void gpio_init(void)
{
int i;
printk(BIOS_INFO, "Setting up the gpio...\n");
for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
struct cygnus_gpio *chip = cygnus_gpio_table + i;
chip->num_banks = (chip->ngpio+NGPIOS_PER_BANK - 1)
/ NGPIOS_PER_BANK;
if (chip->pinmux_is_supported)
chip->pctl_priv = cygnus_pinmux_init();
}
if (IS_ENABLED(CONFIG_CYGNUS_GPIO_TEST))
cygnus_gpio_test();
}
void gpio_free(gpio_t gpio)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
cygnus_gpio_free(chip, gpio_num);
}
void gpio_input(gpio_t gpio)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
if (cygnus_gpio_request(chip, gpio_num) != 0) {
printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
return;
}
cygnus_gpio_direction_input(chip, gpio_num);
}
void gpio_input_pulldown(gpio_t gpio)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
cygnus_gpio_set_pull(chip, gpio_num, 0, 0);
}
void gpio_input_pullup(gpio_t gpio)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
cygnus_gpio_set_pull(chip, gpio_num, 0, 1);
}
int gpio_get(gpio_t gpio)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return -1;
}
return cygnus_gpio_get(chip, gpio_num);
}
void gpio_set(gpio_t gpio, int value)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
cygnus_gpio_set(chip, gpio_num, value);
}
void gpio_output(gpio_t gpio, int value)
{
struct cygnus_gpio *chip;
unsigned gpio_num;
chip = cygnus_get_gpio_core(gpio, &gpio_num);
if (chip == NULL) {
dev_dbg(chip, "unable to find chip for gpio %d", gpio);
return;
}
if (cygnus_gpio_request(chip, gpio_num) != 0) {
printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
return;
}
cygnus_gpio_direction_output(chip, gpio_num, value);
}

759
src/soc/broadcom/cygnus/hw_init.c
View File

@ -1,759 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <console/console.h>
#include <soc/tz.h>
#include <soc/hw_init.h>
/*****************************************************************************
* TrustZone
*****************************************************************************/
#define IHOST_SCU_SECURE_ACCESS 0x19020054
#define SMAU_NIC_IDM_TZ_BASE 0x180150a0
#define SMAU_DDR_TZ_BASE 0x18015200
#define SMAU_FLASH0_TZ_BASE 0x18015300
#define SMAU_FLASH1_TZ_BASE 0x18015308
#define SMAU_FLASH2_TZ_BASE 0x18015310
#define SMAU_FLASH3_TZ_BASE 0x18015318
#define SMAU_TZ_BASE_ENABLE 0x00000001
#define CRMU_IPROC_ADDR_RANGE0_LOW 0x03024c30
#define CRMU_IPROC_ADDR_RANGE0_HIGH 0x03024c34
#define CRMU_ADDR_MASK 0xffffff00
#define CRMU_ADDR_VALID 0x00000001
#define CRMU_ADDR_START 0x03010000
#define CRMU_ADDR_END 0x03100000
static void scu_ns_config(void)
{
/*
* Enable NS SCU access to ARM global timer, private timer, and
* components
*/
write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF);
}
static void smau_ns_config(void)
{
unsigned int val;
/* Disable SMAU NIC IDM TZ */
val = read32((void *)SMAU_NIC_IDM_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_NIC_IDM_TZ_BASE, val);
/*
* Disable DDR TZ base
*
* This means the entire DDR is marked as NONSECURE (NS)
*
* NOTE: In the future, multiple regions of DDR may need to be marked
* as SECURE for secure OS and other TZ usages
*/
val = read32((void *)SMAU_DDR_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_DDR_TZ_BASE, val);
/*
* Disable flash TZ support
*
* The entire flash is currently marked as NS
*
* NOTE: In the future, multiple regions of flash may need to be marked
* as SECURE for secure OS and other TZ firmware/data storage
*/
/* Flash 0: ROM */
val = read32((void *)SMAU_FLASH0_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_FLASH0_TZ_BASE, val);
/* Flash 1: QSPI */
val = read32((void *)SMAU_FLASH1_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_FLASH1_TZ_BASE, val);
/* Flash 2: NAND */
val = read32((void *)SMAU_FLASH2_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_FLASH2_TZ_BASE, val);
/* Flash 3: PNOR */
val = read32((void *)SMAU_FLASH3_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
write32((void *)SMAU_FLASH3_TZ_BASE, val);
}
static void crmu_ns_config(void)
{
/*
* Currently opens up the entire CRMU to allow iPROC NS access
*
* NOTE: In the future, we might want to protect particular CRMU
* sub-blocks to allow SECURE access only. That can be done by
* programming the CRMU IPROC address range registers. Up to 4 access
* windows can be created
*/
write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,
(CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH,
(CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
}
static void tz_init(void)
{
/* Configure the Cygnus for non-secure access */
/* ARM Cortex A9 SCU NS access configuration */
scu_ns_config();
/* SMAU NS related configurations */
smau_ns_config();
/* CRMU NS related configurations */
crmu_ns_config();
/*
* Configure multiple masters and slaves to run in NS
*/
tz_set_non_virtual_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
tz_set_periph_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
tz_set_masters_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
tz_set_wrapper_security(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
TZ_STATE_NON_SECURE);
tz_set_cfg_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
tz_set_ext_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
/* configure sec peripherals to be accessed from non-secure world */
tz_set_sec_periphs_security(0xFFFFFFFF &
~(CYGNUS_sec_periph_APBz_sotp |
CYGNUS_sec_periph_APBz_tzpc),
TZ_STATE_NON_SECURE);
/* default sram to non-secure */
tz_set_sram_sec_region(0);
}
/*****************************************************************************
* DMAC
*****************************************************************************/
#define DMAC_M0_IDM_RESET_CONTROL 0x1810f800
#define DMAC_RESET_MASK 0x00000001
#define DMAC_RESET_TIMEOUT 1000
static void dmac_init(void)
{
unsigned int val, timeout;
/* bring the DMAC block out of reset */
val = read32((void *)DMAC_M0_IDM_RESET_CONTROL);
val |= DMAC_RESET_MASK;
write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
udelay(10);
val &= ~DMAC_RESET_MASK;
write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
timeout = 0;
while (read32((void *)DMAC_M0_IDM_RESET_CONTROL) & DMAC_RESET_MASK) {
udelay(1);
if (timeout++ > DMAC_RESET_TIMEOUT)
die("Failed to bring PL330 DMAC out of reset\n");
}
}
/*****************************************************************************
* Neon
*****************************************************************************/
#define CRU_CONTROL 0x1800e000
#define CRU_CONTROL_NEON_RESET_N 0x00000040
#define CRU_IHOST_PWRDWN_EN 0x1800e004
#define CRU_IHOST_PWRDWN_EN_CLAMPON_NEON 0x00100000
#define CRU_IHOST_PWRDWN_EN_PWRON_NEON 0x00200000
#define CRU_IHOST_PWRDWN_EN_PWROK_NEON 0x00400000
#define CRU_IHOST_PWRDWN_STATUS 0x1800e008
#define CRU_IHOST_PWRDWN_STATUS_PWRON_NEON 0x00200000
#define CRU_IHOST_PWRDWN_STATUS_PWROK_NEON 0x00400000
#define CRU_STATUS_DELAY_US 1
#define CRU_MAX_RETRY_COUNT 10
#define CRU_RETRY_INTVL_US 1
static void neon_init(void)
{
unsigned int i, val;
/* put Neon into reset */
val = read32((void *)CRU_CONTROL);
val &= ~CRU_CONTROL_NEON_RESET_N;
write32((void *)CRU_CONTROL, val);
/* assert the power on register bit */
val = read32((void *)CRU_IHOST_PWRDWN_EN);
val |= CRU_IHOST_PWRDWN_EN_PWRON_NEON;
write32((void *)CRU_IHOST_PWRDWN_EN, val);
/* wait for power on */
i = 0;
while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
CRU_IHOST_PWRDWN_STATUS_PWRON_NEON)) {
udelay(CRU_RETRY_INTVL_US);
if (i++ >= CRU_MAX_RETRY_COUNT)
die("Failed to ack NEON power on\n");
}
udelay(CRU_STATUS_DELAY_US);
/* assert the power ok register bit */
val = read32((void *)CRU_IHOST_PWRDWN_EN);
val |= CRU_IHOST_PWRDWN_EN_PWROK_NEON;
write32((void *)CRU_IHOST_PWRDWN_EN, val);
/* wait for power ok */
i = 0;
while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
CRU_IHOST_PWRDWN_STATUS_PWROK_NEON)) {
udelay(CRU_RETRY_INTVL_US);
if (i++ >= CRU_MAX_RETRY_COUNT)
die("Failed to ack NEON power ok\n");
}
udelay(CRU_STATUS_DELAY_US);
/* clamp off for the NEON block */
val = read32((void *)CRU_IHOST_PWRDWN_EN);
val &= ~CRU_IHOST_PWRDWN_EN_CLAMPON_NEON;
write32((void *)CRU_IHOST_PWRDWN_EN, val);
udelay(CRU_STATUS_DELAY_US);
/* bring NEON out of reset */
val = read32((void *)CRU_CONTROL);
val |= CRU_CONTROL_NEON_RESET_N;
write32((void *)CRU_CONTROL, val);
}
/*****************************************************************************
* PCIe
*****************************************************************************/
#define CRMU_PCIE_CFG 0x0301d0a0
#define PCIE0_LNK_PHY_IDDQ 0x00000004
#define PCIE1_LNK_PHY_IDDQ 0x00000400
static void pcie_init(void)
{
unsigned int val;
/*
* Force all AFEs of both PCIe0 and PCIe1 to be powered down, including
* pad biasing
*
* This brings down the PCIe interfaces to the lowest possible power
* mode
*/
val = read32((void *)CRMU_PCIE_CFG);
val |= PCIE1_LNK_PHY_IDDQ | PCIE0_LNK_PHY_IDDQ;
write32((void *)CRMU_PCIE_CFG, val);
}
/*****************************************************************************
* M0
*****************************************************************************/
#define CRMU_MCU_ACCESS_CONTROL 0x03024c00
#define CRMU_MCU_ACCESS_MODE_SECURE 0x2
static void M0_init(void)
{
/* Set M0 as a secure master */
write32((void *)CRMU_MCU_ACCESS_CONTROL, CRMU_MCU_ACCESS_MODE_SECURE);
}
/*****************************************************************************
* CCU
*****************************************************************************/
#define IHOST_PROC_CLK_WR_ACCESS 0x19000000
#define IHOST_PROC_CLK_POLICY_FREQ 0x19000008
#define IHOST_PROC_CLK_POLICY_CTL 0x1900000c
#define IHOST_PROC_CLK_POLICY0_MASK 0x19000010
#define IHOST_PROC_CLK_POLICY1_MASK 0x19000014
#define IHOST_PROC_CLK_POLICY2_MASK 0x19000018
#define IHOST_PROC_CLK_POLICY3_MASK 0x1900001c
#define IHOST_PROC_CLK_INTEN 0x19000020
#define IHOST_PROC_CLK_INTSTAT 0x19000024
#define IHOST_PROC_CLK_LVM_EN 0x19000034
#define IHOST_PROC_CLK_LVM0_3 0x19000038
#define IHOST_PROC_CLK_LVM4_7 0x1900003c
#define IHOST_PROC_CLK_VLT0_3 0x19000040
#define IHOST_PROC_CLK_VLT4_7 0x19000044
#define IHOST_PROC_CLK_BUS_QUIESC 0x19000100
#define IHOST_PROC_CLK_CORE0_CLKGATE 0x19000200
#define IHOST_PROC_CLK_CORE1_CLKGATE 0x19000204
#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0x19000210
#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0x19000300
#define IHOST_PROC_CLK_APB0_CLKGATE 0x19000400
#define IHOST_PROC_CLK_PL310_DIV 0x19000a00
#define IHOST_PROC_CLK_PL310_TRIGGER 0x19000a04
#define IHOST_PROC_CLK_ARM_SWITCH_DIV 0x19000a08
#define IHOST_PROC_CLK_ARM_SWITCH_TRIGGER 0x19000a0c
#define IHOST_PROC_CLK_APB_DIV 0x19000a10
#define IHOST_PROC_CLK_APB_DIV_TRIGGER 0x19000a14
#define IHOST_PROC_CLK_PLLARMA 0x19000c00
#define IHOST_PROC_CLK_PLLARMB 0x19000c04
#define IHOST_PROC_CLK_PLLARMC 0x19000c08
#define IHOST_PROC_CLK_PLLARMCTRL0 0x19000c0c
#define IHOST_PROC_CLK_PLLARMCTRL1 0x19000c10
#define IHOST_PROC_CLK_PLLARMCTRL2 0x19000c14
#define IHOST_PROC_CLK_PLLARMCTRL3 0x19000c18
#define IHOST_PROC_CLK_PLLARMCTRL4 0x19000c1c
#define IHOST_PROC_CLK_PLLARMCTRL5 0x19000c20
#define IHOST_PROC_CLK_PLLARM_OFFSET 0x19000c24
#define IHOST_PROC_CLK_ARM_DIV 0x19000e00
#define IHOST_PROC_CLK_ARM_SEG_TRG 0x19000e04
#define IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE 0x19000e08
#define IHOST_PROC_CLK_PLL_DEBUG 0x19000e10
#define IHOST_PROC_CLK_ACTIVITY_MON1 0x19000e20
#define IHOST_PROC_CLK_ACTIVITY_MON2 0x19000e24
#define IHOST_PROC_CLK_CLKGATE_DBG 0x19000e40
#define IHOST_PROC_CLK_APB_CLKGATE_DBG1 0x19000e48
#define IHOST_PROC_CLK_CLKMON 0x19000e64
#define IHOST_PROC_CLK_POLICY_DBG 0x19000ec0
#define IHOST_PROC_CLK_TGTMASK_DBG1 0x19000ec4
#define IHOST_PROC_RST_WR_ACCESS 0x19000f00
#define IHOST_PROC_RST_SOFT_RSTN 0x19000f04
#define IHOST_PROC_RST_A9_CORE_SOFT_RSTN 0x19000f08
#define WR_ACCESS_PRIVATE_ACCESS_MODE 0x80000000
static uint32_t ccu_reg[] = {
IHOST_PROC_CLK_WR_ACCESS,
IHOST_PROC_CLK_POLICY_FREQ,
IHOST_PROC_CLK_POLICY_CTL,
IHOST_PROC_CLK_POLICY0_MASK,
IHOST_PROC_CLK_POLICY1_MASK,
IHOST_PROC_CLK_POLICY2_MASK,
IHOST_PROC_CLK_POLICY3_MASK,
IHOST_PROC_CLK_INTEN,
IHOST_PROC_CLK_INTSTAT,
IHOST_PROC_CLK_LVM_EN,
IHOST_PROC_CLK_LVM0_3,
IHOST_PROC_CLK_LVM4_7,
IHOST_PROC_CLK_VLT0_3,
IHOST_PROC_CLK_VLT4_7,
IHOST_PROC_CLK_BUS_QUIESC,
IHOST_PROC_CLK_CORE0_CLKGATE,
IHOST_PROC_CLK_CORE1_CLKGATE,
IHOST_PROC_CLK_ARM_SWITCH_CLKGATE,
IHOST_PROC_CLK_ARM_PERIPH_CLKGATE,
IHOST_PROC_CLK_APB0_CLKGATE,
IHOST_PROC_CLK_PL310_DIV,
IHOST_PROC_CLK_PL310_TRIGGER,
IHOST_PROC_CLK_ARM_SWITCH_DIV,
IHOST_PROC_CLK_ARM_SWITCH_TRIGGER,
IHOST_PROC_CLK_APB_DIV,
IHOST_PROC_CLK_APB_DIV_TRIGGER,
IHOST_PROC_CLK_PLLARMA,
IHOST_PROC_CLK_PLLARMB,
IHOST_PROC_CLK_PLLARMC,
IHOST_PROC_CLK_PLLARMCTRL0,
IHOST_PROC_CLK_PLLARMCTRL1,
IHOST_PROC_CLK_PLLARMCTRL2,
IHOST_PROC_CLK_PLLARMCTRL3,
IHOST_PROC_CLK_PLLARMCTRL4,
IHOST_PROC_CLK_PLLARMCTRL5,
IHOST_PROC_CLK_PLLARM_OFFSET,
IHOST_PROC_CLK_ARM_DIV,
IHOST_PROC_CLK_ARM_SEG_TRG,
IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE,
IHOST_PROC_CLK_PLL_DEBUG,
IHOST_PROC_CLK_ACTIVITY_MON1,
IHOST_PROC_CLK_ACTIVITY_MON2,
IHOST_PROC_CLK_CLKGATE_DBG,
IHOST_PROC_CLK_APB_CLKGATE_DBG1,
IHOST_PROC_CLK_CLKMON,
IHOST_PROC_CLK_POLICY_DBG,
IHOST_PROC_CLK_TGTMASK_DBG1,
IHOST_PROC_RST_WR_ACCESS,
IHOST_PROC_RST_SOFT_RSTN,
IHOST_PROC_RST_A9_CORE_SOFT_RSTN
};
#define CCU_REG_TABLE_SIZE (sizeof(ccu_reg)/sizeof(ccu_reg[0]))
/* Set priv_access_mode field to unrestricted (0) */
static void ccu_init(void)
{
uint32_t val;
uint32_t i;
for (i = 0; i < CCU_REG_TABLE_SIZE; i++) {
val = read32((void *)(ccu_reg[i]));
val &= ~WR_ACCESS_PRIVATE_ACCESS_MODE;
write32((void *)(ccu_reg[i]), val);
}
}
/*****************************************************************************
* LCD
*****************************************************************************/
#define ASIU_TOP_CLK_GATING_CTRL 0x180aa024
#define ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN 0x00000010
#define ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN 0x00000008
#define ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN 0x00000001
#define ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN 0x00000002
static void lcd_init(void)
{
unsigned int val;
/* make sure the LCD clock is ungated */
val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN;
write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
}
/*******************************************************************
* Default priority settings in Cygnus
*
* Master Name Default Priority
* ==================== =================
* ihost_m0 12
* mhost0_m0 12
* mhost1_m0 ` 12
* pcie0_m0 9
* pcie0_m1 9
* cmicd_m0 7
* amac_m0 7
* amac_m1 7
* ext_m0 (LCD) 5
* ext_m1 (V3D) 5
* sdio_m0 3
* sdio_m1 3
* usb2h_m0 3
* usb2d_m0 3
* dmu_m0 3
* a9jtag_m0 0
*
*****************************************************************************/
#define AXIIC_EXT_M0_READ_QOS 0x1a057100
#define AXIIC_EXT_M0_READ_MASK 0x0000000f
#define AXIIC_EXT_M0_WRITE_QOS 0x1a057104
#define AXIIC_EXT_M0_WRITE_MASK 0x0000000f
static void lcd_qos_init(unsigned int qos)
{
unsigned int val;
val = read32((void *)AXIIC_EXT_M0_READ_QOS);
val &= ~AXIIC_EXT_M0_READ_MASK;
val |= (qos & AXIIC_EXT_M0_READ_MASK);
write32((void *)AXIIC_EXT_M0_READ_QOS, val);
val = read32((void *)AXIIC_EXT_M0_WRITE_QOS);
val &= ~AXIIC_EXT_M0_WRITE_MASK;
val |= (qos & AXIIC_EXT_M0_WRITE_MASK);
write32((void *)AXIIC_EXT_M0_WRITE_QOS, val);
}
/*****************************************************************************
* V3D
*****************************************************************************/
static void v3d_init(void)
{
unsigned int val;
/* make sure the V3D clock is ungated */
val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN |
ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN;
write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
}
/*****************************************************************************
* Audio
*****************************************************************************/
#define CRMU_PLL_AON_CTRL 0x0301c020
#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL 0x00000800
#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG 0x00000400
#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO 0x00000200
#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN 0x00000100
static void audio_init(void)
{
unsigned int val;
/* Ungate (enable) audio clock. */
val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN;
write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
/* Power on audio GEN PLL, LDO, and BG. Input isolation = normal. */
val = read32((void *)CRMU_PLL_AON_CTRL);
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG;
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO;
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL;
val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN;
write32((void *)CRMU_PLL_AON_CTRL, val);
}
/*****************************************************************************
* SDIO
*****************************************************************************/
#define CRMU_SDIO_1P8_FAIL_CONTROL 0x0301c0a0
#define UHS1_18V_VREG_FAIL 0x00000001
#define SDIO_IDM0_IO_CONTROL_DIRECT 0x18116408
#define SDIO_IDM1_IO_CONTROL_DIRECT 0x18117408
#define SDIO_CMD_COMFLICT_DISABLE 0x00400000
#define SDIO_FEEDBACK_CLK_EN 0x00200000
#define SDIO_CLK_ENABLE 0x00000001
#define CDRU_SDIO0_IO_CONTROL 0x0301d144
#define CDRU_SDIO1_IO_CONTROL 0x0301d140
#define INPUT_DISABLE 0x00000080
#define SLEW_RATE_ENABLE 0x00000040
#define PULL_UP_ENABLE 0x00000020
#define PULL_DOWN_ENABLE 0x00000010
#define HYSTERESIS_ENABLE 0x00000008
#define SDIO_DEFAULT_DRIVE_STRENGTH 0x4 /* 8 mA */
#define SDIO_IDM0_IDM_RESET_CONTROL 0x18116800
#define SDIO_IDM1_IDM_RESET_CONTROL 0x18117800
#define SDIO_RESET_MASK 0x00000001
#define SDIO_RESET_TIMEOUT 1000
#define CRMU_SDIO_CONTROL0 0x0301d088
#define CRMU_SDIO_CONTROL1 0x0301d08c
#define CRMU_SDIO_CONTROL2 0x0301d090
#define CRMU_SDIO_CONTROL3 0x0301d094
#define CRMU_SDIO_CONTROL4 0x0301d098
#define CRMU_SDIO_CONTROL5 0x0301d09c
/*
* SDIO_CAPS_L
*
* Field Bit(s)
* ===========================
* DDR50 31
* SDR104 30
* SDR50 29
* SLOTTYPE 28:27
* ASYNCHIRQ 26
* SYSBUS64 25
* V18 24
* V3 23
* V33 22
* SUPRSM 21
* SDMA 20
* HSPEED 19
* ADMA2 18
* EXTBUSMED 17
* MAXBLK 16:15
* BCLK 14:7
* TOUT 6
* TOUTFREQ 5:0
*/
#define SDIO_CAPS_L 0xA17C0000
/*
* SDIO_CAPS_H
*
* Field Bit(s)
* ===========================
* reserved 31:20
* SPIBLOCKMODE 19
* SPIMODE_CAP 18
* CLOCKMULT 17:10
* RETUNE_MODE 9:8
* USETUNE_SDR50 7
* TMRCNT_RETUNE 6:3
* DRVR_TYPED 2
* DRVR_TYPEC 1
* DRVR_TYPEA 0
*/
#define SDIO_CAPS_H 0x000C0087
/*
* Preset value
*
* Field Bit(s)
* ===========================
* Driver Strength 12:11
* Clock Generator 10
* SDCLK Frequeency 9:0
*/
/*
* SDIO_PRESETVAL1
*
* Field Bit(s) Description
* ============================================================
* DDR50_PRESET 25:13 Preset Value for DDR50
* DEFAULT_PRESET 12:0 Preset Value for Default Speed
*/
#define SDIO_PRESETVAL1 0x01004004
/*
* SDIO_PRESETVAL2
*
* Field Bit(s) Description
* ============================================================
* HIGH_SPEED_PRESET 25:13 Preset Value for High Speed
* INIT_PRESET 12:0 Preset Value for Initialization
*/
#define SDIO_PRESETVAL2 0x01004100
/*
* SDIO_PRESETVAL3
*
* Field Bit(s) Description
* ============================================================
* SDR104_PRESET 25:13 Preset Value for SDR104
* SDR12_PRESET 12:0 Preset Value for SDR12
*/
#define SDIO_PRESETVAL3 0x00000004
/*
* SDIO_PRESETVAL4
*
* Field Bit(s) Description
* ============================================================
* SDR25_PRESET 25:13 Preset Value for SDR25
* SDR50_PRESET 12:0 Preset Value for SDR50
*/
#define SDIO_PRESETVAL4 0x01005001
static void sdio_ctrl_init(unsigned int idx)
{
unsigned int sdio_idm_io_control_direct_reg;
unsigned int cdru_sdio_io_control_reg;
unsigned int sdio_idm_reset_control_reg;
unsigned int val, timeout;
switch (idx) {
case 0:
sdio_idm_io_control_direct_reg = SDIO_IDM0_IO_CONTROL_DIRECT;
cdru_sdio_io_control_reg = CDRU_SDIO0_IO_CONTROL;
sdio_idm_reset_control_reg = SDIO_IDM0_IDM_RESET_CONTROL;
break;
case 1:
sdio_idm_io_control_direct_reg = SDIO_IDM1_IO_CONTROL_DIRECT;
cdru_sdio_io_control_reg = CDRU_SDIO1_IO_CONTROL;
sdio_idm_reset_control_reg = SDIO_IDM1_IDM_RESET_CONTROL;
break;
default:
return;
}
/*
* Disable the cmd conflict error interrupt and enable feedback clock
*/
val = read32((void *)sdio_idm_io_control_direct_reg);
val |= SDIO_CMD_COMFLICT_DISABLE | SDIO_FEEDBACK_CLK_EN |
SDIO_CLK_ENABLE;
write32((void *)sdio_idm_io_control_direct_reg, val);
/*
* Set drive strength, enable hysteresis and slew rate control
*/
val = SDIO_DEFAULT_DRIVE_STRENGTH |
HYSTERESIS_ENABLE | SLEW_RATE_ENABLE;
write32((void *)cdru_sdio_io_control_reg, val);
/* Reset SDIO controller */
val = read32((void *)sdio_idm_reset_control_reg);
val |= SDIO_RESET_MASK;
write32((void *)sdio_idm_reset_control_reg, SDIO_RESET_MASK);
udelay(10);
val &= ~SDIO_RESET_MASK;
write32((void *)sdio_idm_reset_control_reg, val);
timeout = 0;
while (read32((void *)sdio_idm_reset_control_reg) & SDIO_RESET_MASK) {
udelay(1);
if (timeout++ > SDIO_RESET_TIMEOUT)
die("Failed to bring SDIO out of reset\n");
}
}
static void sdio_init(void)
{
unsigned int val;
/*
* Configure SDIO host controller capabilities
* (common setting for all SDIO controllers)
*/
write32((void *)CRMU_SDIO_CONTROL0, SDIO_CAPS_H);
write32((void *)CRMU_SDIO_CONTROL1, SDIO_CAPS_L);
/*
* Configure SDIO host controller preset values
* (common setting for all SDIO controllers)
*/
write32((void *)CRMU_SDIO_CONTROL2, SDIO_PRESETVAL1);
write32((void *)CRMU_SDIO_CONTROL3, SDIO_PRESETVAL2);
write32((void *)CRMU_SDIO_CONTROL4, SDIO_PRESETVAL3);
write32((void *)CRMU_SDIO_CONTROL5, SDIO_PRESETVAL4);
/*
* The sdhci driver attempts to change the SDIO IO voltage for UHS-I
* cards by setting the EN1P8V in control2 register then checks the
* outcome by reading it back.
* Cygnus does not have an internal regulator for the SDIO IO voltage
* but can be configured to indicate success (leave EN1P8V set)
* or failure (clear EN1P8V).
*
* Clear CRMU_SDIO_UHS1_18V_VREG_FAIL in CRMU_SDIO_1P8_FAIL_CONTROL
* register to indicate success.
* (common setting for all SDIO controllers)
*/
val = read32((void *)CRMU_SDIO_1P8_FAIL_CONTROL);
val &= ~UHS1_18V_VREG_FAIL;
write32((void *)CRMU_SDIO_1P8_FAIL_CONTROL, val);
/*
* Initialize each SDIO controller
*/
sdio_ctrl_init(0);
sdio_ctrl_init(1);
}
void hw_init(void)
{
tz_init();
printk(BIOS_INFO, "trustzone initialized\n");
dmac_init();
printk(BIOS_INFO, "PL330 DMAC initialized\n");
lcd_init();
lcd_qos_init(15);
printk(BIOS_INFO, "LCD initialized\n");
v3d_init();
printk(BIOS_INFO, "V3D initialized\n");
audio_init();
printk(BIOS_INFO, "audio initialized\n");
neon_init();
printk(BIOS_INFO, "neon initialized\n");
pcie_init();
printk(BIOS_INFO, "PCIe initialized\n");
M0_init();
printk(BIOS_INFO, "M0 initialized\n");
ccu_init();
printk(BIOS_INFO, "CCU initialized\n");
sdio_init();
printk(BIOS_INFO, "SDIO initialized\n");
}

266
src/soc/broadcom/cygnus/i2c.c
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@ -1,266 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <device/i2c_simple.h>
#include <soc/i2c.h>
struct cygnus_i2c_regs {
u32 i2c_con;
u32 i2c_timing_con;
u32 i2c_addr;
u32 i2c_fifo_master;
u32 i2c_fifo_slave;
u32 i2c_bit_bang;
u32 reserved0[(0x30 - 0x18) / 4];
u32 i2c_master_comm;
u32 i2c_slave_comm;
u32 i2c_int_en;
u32 i2c_int_status;
u32 i2c_master_data_wr;
u32 i2c_master_data_rd;
u32 i2c_slave_data_wr;
u32 i2c_slave_data_rd;
u32 reserved1[(0xb0 - 0x50) / 4];
u32 i2c_timing_con2;
};
static struct cygnus_i2c_regs *i2c_bus[] = {
(struct cygnus_i2c_regs *)0x18008000,
(struct cygnus_i2c_regs *)0x1800b000,
};
#define I2C_TIMEOUT_US 100000 /* 100ms */
#define I2C_FIFO_MAX_SIZE 64
#define ETIMEDOUT 1
#define EINVAL 2
#define EBUSY 3
/* Configuration (0x0) */
#define I2C_SMB_RESET (1 << 31)
#define I2C_SMB_EN (1 << 30)
/* Timing configuration (0x4) */
#define I2C_MODE_400 (1 << 31)
/* Master FIFO control (0xc) */
#define I2C_MASTER_RX_FIFO_FLUSH (1 << 31)
#define I2C_MASTER_TX_FIFO_FLUSH (1 << 30)
/* Master command (0x30) */
#define I2C_MASTER_START_BUSY (1 << 31)
#define I2C_MASTER_STATUS_SFT 25
#define I2C_MASTER_STATUS_MASK (0x7 << I2C_MASTER_STATUS_SFT)
#define I2C_MASTER_PROT_SFT 9
#define I2C_MASTER_PROT_BLK_WR (0x7 << I2C_MASTER_PROT_SFT)
#define I2C_MASTER_PROT_BLK_RD (0x8 << I2C_MASTER_PROT_SFT)
/* Master data write (0x40) */
#define I2C_MASTER_WR_STATUS (1 << 31)
/* Master data read (0x44) */
#define I2C_MASTER_RD_DATA_MASK 0xff
static unsigned int i2c_bus_busy(struct cygnus_i2c_regs *reg_addr)
{
return read32(&reg_addr->i2c_master_comm) & I2C_MASTER_START_BUSY;
}
static int i2c_wait_bus_busy(struct cygnus_i2c_regs *reg_addr)
{
int timeout = I2C_TIMEOUT_US;
while (timeout--) {
if (!i2c_bus_busy(reg_addr))
break;
udelay(1);
}
if (timeout <= 0)
return ETIMEDOUT;
return 0;
}
static void i2c_flush_fifo(struct cygnus_i2c_regs *reg_addr)
{
write32(&reg_addr->i2c_fifo_master,
I2C_MASTER_RX_FIFO_FLUSH | I2C_MASTER_TX_FIFO_FLUSH);
}
static int i2c_write(struct cygnus_i2c_regs *reg_addr,
struct i2c_msg *segment)
{
uint8_t *data = segment->buf;
unsigned int val, status;
int i, ret;
write32(&reg_addr->i2c_master_data_wr, segment->slave << 1);
for (i = 0; i < segment->len; i++) {
val = data[i];
/* mark the last byte */
if (i == segment->len - 1)
val |= I2C_MASTER_WR_STATUS;
write32(&reg_addr->i2c_master_data_wr, val);
}
if (segment->len == 0)
write32(&reg_addr->i2c_master_data_wr, I2C_MASTER_WR_STATUS);
/*
* Now we can activate the transfer.
*/
write32(&reg_addr->i2c_master_comm,
I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_WR);
ret = i2c_wait_bus_busy(reg_addr);
if (ret) {
printk(BIOS_ERR, "I2C bus timeout\n");
goto flush_fifo;
}
/* check transaction successful */
status = read32(&reg_addr->i2c_master_comm);
ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
if (ret) {
printk(BIOS_ERR, "I2C write error %u\n", status);
goto flush_fifo;
}
return 0;
flush_fifo:
i2c_flush_fifo(reg_addr);
return ret;
}
static int i2c_read(struct cygnus_i2c_regs *reg_addr, struct i2c_msg *segment)
{
uint8_t *data = segment->buf;
int i, ret;
unsigned int status;
write32(&reg_addr->i2c_master_data_wr, segment->slave << 1 | 1);
/*
* Now we can activate the transfer. Specify the number of bytes to read
*/
write32(&reg_addr->i2c_master_comm,
I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_RD | segment->len);
ret = i2c_wait_bus_busy(reg_addr);
if (ret) {
printk(BIOS_ERR, "I2C bus timeout\n");
goto flush_fifo;
}
/* check transaction successful */
status = read32(&reg_addr->i2c_master_comm);
ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
if (ret) {
printk(BIOS_ERR, "I2C read error %u\n", status);
goto flush_fifo;
}
for (i = 0; i < segment->len; i++)
data[i] = read32(&reg_addr->i2c_master_data_rd) &
I2C_MASTER_RD_DATA_MASK;
return 0;
flush_fifo:
i2c_flush_fifo(reg_addr);
return ret;
}
static int i2c_do_xfer(struct cygnus_i2c_regs *reg_addr,
struct i2c_msg *segment)
{
int ret;
if (segment->len > I2C_FIFO_MAX_SIZE - 1) {
printk(BIOS_ERR,
"I2C transfer error: segment size (%d) is larger than limit (%d)\n",
segment->len, I2C_FIFO_MAX_SIZE);
return EINVAL;
}
if (i2c_bus_busy(reg_addr)) {
printk(BIOS_WARNING, "I2C transfer error: bus is busy\n");
return EBUSY;
}
if (segment->flags & I2C_M_RD)
ret = i2c_read(reg_addr, segment);
else
ret = i2c_write(reg_addr, segment);
return ret;
}
int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
int seg_count)
{
int i;
int res = 0;
struct cygnus_i2c_regs *regs = i2c_bus[bus];
struct i2c_msg *seg = segments;
for (i = 0; i < seg_count; i++, seg++) {
res = i2c_do_xfer(regs, seg);
if (res)
break;
}
return res;
}
void i2c_init(unsigned int bus, unsigned int hz)
{
struct cygnus_i2c_regs *regs = i2c_bus[bus];
assert(bus >= 0 && bus <= 1);
setbits_le32(&regs->i2c_con, I2C_SMB_RESET);
udelay(100); /* wait 100 usec per spec */
clrbits_le32(&regs->i2c_con, I2C_SMB_RESET);
switch (hz) {
case 100000:
clrbits_le32(&regs->i2c_timing_con, I2C_MODE_400);
break;
case 400000:
setbits_le32(&regs->i2c_timing_con, I2C_MODE_400);
break;
default:
printk(BIOS_ERR, "I2C bus does not support frequency %d Hz\n",
hz);
break;
}
i2c_flush_fifo(regs);
/* disable all interrupts */
write32(&regs->i2c_int_en, 0);
/* clear all pending interrupts */
write32(&regs->i2c_int_status, 0xffffffff);
write32(&regs->i2c_con, I2C_SMB_EN);
}

26
src/soc/broadcom/cygnus/include/soc/addressmap.h
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@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
#define __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
#define IPROC_PERIPH_BASE 0x19020000
#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
#define IPROC_QSPI_BASE 0x18047000
#define IPROC_IOMUX_OVERRIDE_BASE 0x0301D24C
#endif /* __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__ */

36
src/soc/broadcom/cygnus/include/soc/config.h
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@ -1,36 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_CONFIG_H__
#define __SOC_BROADCOM_CYGNUS_CONFIG_H__
#include <stdint.h>
#include <string.h>
#include <soc/halapis/ddr_regs.h>
/* DDR shmoo Parameters */
#define SDI_INTERFACE_BITWIDTH 16
#define SDI_NUM_COLUMNS 1024
#define SDI_NUM_BANKS 8
#ifdef DDR3_SIZE_512MB
#define SDI_NUM_ROWS 32768
#else
#define SDI_NUM_ROWS 65536
#endif
/* Idle count (in units of 1024 cycles) before auto entering self-refresh */
#define DDR_AUTO_SELF_REFRESH_IDLE_COUNT 16
#endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */

21
src/soc/broadcom/cygnus/include/soc/cygnus.h
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@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_H__
#define __SOC_BROADCOM_CYGNUS_H__
void usb_init(void);
#endif

43
src/soc/broadcom/cygnus/include/soc/cygnus_types.h
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@ -1,43 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
#define __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
#include <stdint.h>
#include <types.h>
#ifndef TRUE
#define TRUE (1 == 1)
#endif
#ifndef FALSE
#define FALSE (1 == 0)
#endif
#ifndef NULL
#define NULL 0
#endif
/**********************************************************************
* Basic types
**********************************************************************/
typedef uint8_t uint8;
typedef int8_t int8;
typedef uint16_t uint16;
typedef int16_t int16;
typedef int32_t int32;
typedef uint32_t uint32;
#endif

159
src/soc/broadcom/cygnus/include/soc/ddr_bist.h
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@ -1,159 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
#define __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
#include <soc/config.h>
#define SOC_E_NONE (0)
#define SOC_E_FAIL (-1)
#define SOC_E_INTERNAL (-2)
#define SOC_E_TIMEOUT (-3)
#define SOC_E_PARAM (-4)
#define SOC_E_MEMORY (-5)
#define SOC_E_UNAVAIL (-6)
#define SOC_E_CONFIG (-7)
#define SOC_DDR3_CLOCK_MHZ(unit) iproc_get_ddr3_clock_mhz(unit)
#define DDR_SHMOO_PARAM_MEM_PTR (0x1b000000) /*size ~0x300 */
#define DDR_SHMOO_VREFW_MEM_PTR (0x50000000) /* size ~0x30000 */
#define SOC_DDR3_NUM_MEMORIES (1)
/* Convenience Macros - Arad Memory Controller - Recheck when MemC files change */
enum drc_reg_set {
DRC_BIST_CONFIGr = 0,
DRC_BIST_CONFIG2r,
DRC_BIST_GENERAL_CONFIGURATIONSr,
DRC_BIST_CONFIGURATIONSr,
DRC_BIST_NUMBER_OF_ACTIONSr,
DRC_BIST_START_ADDRESSr,
DRC_BIST_END_ADDRESSr,
DRC_BIST_SINGLE_BIT_MASKr,
DRC_BIST_PATTERN_WORD_7r,
DRC_BIST_PATTERN_WORD_6r,
DRC_BIST_PATTERN_WORD_5r,
DRC_BIST_PATTERN_WORD_4r,
DRC_BIST_PATTERN_WORD_3r,
DRC_BIST_PATTERN_WORD_2r,
DRC_BIST_PATTERN_WORD_1r,
DRC_BIST_PATTERN_WORD_0r,
DRC_BIST_FULL_MASK_WORD_7r,
DRC_BIST_FULL_MASK_WORD_6r,
DRC_BIST_FULL_MASK_WORD_5r,
DRC_BIST_FULL_MASK_WORD_4r,
DRC_BIST_FULL_MASK_WORD_3r,
DRC_BIST_FULL_MASK_WORD_2r,
DRC_BIST_FULL_MASK_WORD_1r,
DRC_BIST_FULL_MASK_WORD_0r,
DRC_BIST_STATUSESr,
DRC_BIST_FULL_MASK_ERROR_COUNTERr,
DRC_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr,
DRC_BIST_ERROR_OCCURREDr,
DRC_BIST_GLOBAL_ERROR_COUNTERr,
DRC_BIST_LAST_ADDR_ERRr,
DRC_BIST_LAST_DATA_ERR_WORD_7r,
DRC_BIST_LAST_DATA_ERR_WORD_6r,
DRC_BIST_LAST_DATA_ERR_WORD_5r,
DRC_BIST_LAST_DATA_ERR_WORD_4r,
DRC_BIST_LAST_DATA_ERR_WORD_3r,
DRC_BIST_LAST_DATA_ERR_WORD_2r,
DRC_BIST_LAST_DATA_ERR_WORD_1r,
DRC_BIST_LAST_DATA_ERR_WORD_0r
};
#define DRCA DDR_BistConfig
#define DRCB DDR_BistConfig
#define DRCC DDR_BistConfig
#define DRCD DDR_BistConfig
#define DRCE DDR_BistConfig
#define DRCF DDR_BistConfig
#define DRCG DDR_BistConfig
#define DRCH DDR_BistConfig
#define DRCALL DDR_BistConfig
#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_SHIFT 26
#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_WIDTH 6
#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_SHIFT 25
#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_SHIFT 24
#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_SHIFT 23
#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_SHIFT 22
#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_SHIFT 21
#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_SHIFT 20
#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_SHIFT 19
#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_SHIFT 18
#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_SHIFT 17
#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_SHIFT 16
#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_WIDTH 1
#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_SHIFT 8
#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_WIDTH 8
#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_SHIFT 0
#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_WIDTH 8
#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_SHIFT 0
#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_WIDTH 32
#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_SHIFT 0
#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_WIDTH 26
#define DRCA_BIST_START_ADDRESSr_RESERVED_SHIFT 26
#define DRCA_BIST_START_ADDRESSr_RESERVED_WIDTH 6
#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_SHIFT 0
#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_WIDTH 26
#define DRCA_BIST_END_ADDRESSr_RESERVED_SHIFT 26
#define DRCA_BIST_END_ADDRESSr_RESERVED_WIDTH 6
#define DRCA_BIST_STATUSESr_RESERVED_SHIFT 4
#define DRCA_BIST_STATUSESr_RESERVED_WIDTH 28
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_SHIFT 3
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_WIDTH 1
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_SHIFT 2
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_WIDTH 1
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_SHIFT 1
#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_WIDTH 1
#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_SHIFT 0
#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_WIDTH 1
#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_SHIFT 0
#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_WIDTH 32
#define soc_reg_field_set(unit, r, m, f, data) \
(*(m) = ((*(m) & ~(((1 << r##_##f##_WIDTH) - 1) << r##_##f##_SHIFT)) | ((data & ((1 << r##_##f##_WIDTH) - 1)) << r##_##f##_SHIFT)))
#define soc_reg_field_get(unit, r, m, f) \
((m >> r##_##f##_SHIFT) & ((1 << r##_##f##_WIDTH) - 1))
#define DRC_REG_READ(unit, channel, reg, rvp) \
soc_reg32_get((volatile uint32*)(channel + 4 * reg), rvp)
#define DRC_REG_WRITE(unit, channel, reg, rv) \
soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv)
#endif /* __SOC_BROADCOM_CYGNUS_DDR_BIST_H__ */
/* End of File */

37
src/soc/broadcom/cygnus/include/soc/gpio.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_GPIO_H__
#define __SOC_BROADCOM_CYGNUS_GPIO_H__
#include <types.h>
#define ENOTSUPP 524 /* Operation is not supported */
/* Supported GPIO types. Not all of these types are supported on all boards. */
enum iproc_gpio_types {
IPROC_GPIO_CCA_ID,
IPROC_GPIO_CMICM_ID,
IPROC_GPIO_ASIU_ID
};
typedef u32 gpio_t;
void *cygnus_pinmux_init(void);
int cygnus_gpio_request_enable(void *priv, unsigned pin);
void cygnus_gpio_disable_free(void *priv, unsigned pin);
void gpio_init(void);
void gpio_free(gpio_t gpio);
#endif /* __SOC_BROADCOM_CYGNUS_GPIO_H__ */

1074
src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
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19
src/soc/broadcom/cygnus/include/soc/hw_init.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_HW_INIT_H__
#define __SOC_BROADCOM_CYGNUS_HW_INIT_H__
void hw_init(void);
#endif

21
src/soc/broadcom/cygnus/include/soc/i2c.h
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_I2C_H__
#define __SOC_BROADCOM_CYGNUS_I2C_H__
void i2c_init(unsigned int bus, unsigned int hz);
#endif /* __SOC_BROADCOM_CYGNUS_I2C_H__ */

41
src/soc/broadcom/cygnus/include/soc/memlayout.ld
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
SRAM_START(0x02000000)
REGION(reserved_for_system_status, 0x02000000, 4K, 4)
TTB(0x02004000, 16K) /* must be aligned to 16K */
TTB_SUBTABLES(0x02008000, 1K)
REGION(reserved_for_maskrom, 0x02009400, 4K, 4)
BOOTBLOCK(0x0200A440, 18K)
PRERAM_CBMEM_CONSOLE(0x0200F000, 2K)
VBOOT2_WORK(0x0200f800, 16K)
OVERLAP_VERSTAGE_ROMSTAGE(0x02013800, 122K)
PRERAM_CBFS_CACHE(0x02032000, 1K)
TIMESTAMP(0x02032400, 1K)
STACK(0x02033000, 12K)
REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4)
SRAM_END(0x02040000)
DRAM_START(0x60000000)
RAMSTAGE(0x60000000, 128K)
POSTRAM_CBFS_CACHE(0x60100000, 1M)
DMA_COHERENT(0x60200000, 2M)
}

143
src/soc/broadcom/cygnus/include/soc/ns16550.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 Flying Pig Systems
* Copyright (C) 2005 Wind River Systems
* Copyright (C) 2009 DENX Software Engineering GmbH
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
struct ns16550 {
union {
uint32_t thr; /* Transmit holding register. */
uint32_t rbr; /* Receive buffer register. */
uint32_t dll; /* Divisor latch lsb. */
};
union {
uint32_t ier; /* Interrupt enable register. */
uint32_t dlm; /* Divisor latch msb. */
};
union {
uint32_t iir; /* Interrupt identification register. */
uint32_t fcr; /* FIFO control register. */
};
uint32_t lcr; /* 3 */
uint32_t mcr; /* 4 */
uint32_t lsr; /* 5 */
uint32_t msr; /* 6 */
uint32_t spr; /* 7 */
uint32_t mdr1; /* 8 */
uint32_t reg9; /* 9 */
uint32_t regA; /* A */
uint32_t regB; /* B */
uint32_t regC; /* C */
uint32_t regD; /* D */
uint32_t regE; /* E */
uint32_t uasr; /* F */
uint32_t scr; /* 10*/
uint32_t ssr; /* 11*/
uint32_t reg12; /* 12*/
uint32_t osc_12m_sel; /* 13*/
};
/*
* These are the definitions for the FIFO Control Register
*/
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_DTR 0x01 /* DTR */
#define UART_MCR_RTS 0x02 /* RTS */
#define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
#define UART_LCR_PEN 0x08 /* Parity eneble */
#define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */
#define UART_LCR_BKSE 0x80 /* Bank select enable */
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_OE 0x02 /* Overrun */
#define UART_LSR_PE 0x04 /* Parity error */
#define UART_LSR_FE 0x08 /* Framing error */
#define UART_LSR_BI 0x10 /* Break */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
#define UART_LSR_TEMT 0x40 /* Xmitter empty */
#define UART_LSR_ERR 0x80 /* Error */
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
/* useful defaults for LCR: 8 data, 1 stop, no parity */
#define UART_LCR_8N1 0x03

181
src/soc/broadcom/cygnus/include/soc/reg_utils.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_REG_UTILS__
#define __SOC_BROADCOM_CYGNUS_REG_UTILS__
/* ---- Include Files ---------------------------------------------------- */
#include <stdint.h>
/* ---- Public Constants and Types --------------------------------------- */
#define __REG32(x) (*((volatile uint32_t *)(x)))
#define __REG16(x) (*((volatile uint16_t *)(x)))
#define __REG8(x) (*((volatile uint8_t *) (x)))
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
/****************************************************************************/
/*
* 32-bit register access functions
*/
/****************************************************************************/
extern uint32_t reg_debug;
#define REG_DEBUG(val) (reg_debug = val)
static inline void
reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & ~(value)));
#endif
*reg &= ~(value);
}
static inline void
reg32_set_bits(volatile uint32_t *reg, uint32_t value)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg | value));
#endif
*reg |= value;
}
static inline void
reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg ^ value));
#endif
*reg ^= value;
}
static inline void
reg32_write_masked(volatile uint32_t *reg, uint32_t mask, uint32_t value)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & (~mask)) | (value & mask));
#endif
*reg = (*reg & (~mask)) | (value & mask);
}
static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x, 0x%x)\n", __FUNCTION__, (uint32_t)reg, value);
#endif
*reg = value;
}
static inline uint32_t
reg32_read(volatile uint32_t *reg)
{
#ifdef DEBUG_REG
if (reg_debug)
printf("%s reg (0x%x): 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg);
#endif
return *reg;
}
/****************************************************************************/
/*
* 16-bit register access functions
*/
/****************************************************************************/
static inline void
reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
{
*reg &= ~(value);
}
static inline void
reg16_set_bits(volatile uint16_t *reg, uint16_t value)
{
*reg |= value;
}
static inline void
reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
{
*reg ^= value;
}
static inline void
reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
{
*reg = (*reg & (~mask)) | (value & mask);
}
static inline void
reg16_write(volatile uint16_t *reg, uint16_t value)
{
*reg = value;
}
static inline uint16_t
reg16_read(volatile uint16_t *reg)
{
return *reg;
}
/****************************************************************************/
/*
* 8-bit register access functions
*/
/****************************************************************************/
static inline void
reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
{
*reg &= ~(value);
}
static inline void
reg8_set_bits(volatile uint8_t *reg, uint8_t value)
{
*reg |= value;
}
static inline void
reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
{
*reg ^= value;
}
static inline void
reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
{
*reg = (*reg & (~mask)) | (value & mask);
}
static inline void
reg8_write(volatile uint8_t *reg, uint8_t value)
{
*reg = value;
}
static inline uint8_t
reg8_read(volatile uint8_t *reg)
{
return *reg;
}
#endif /* __SOC_BROADCOM_CYGNUS_REG_UTILS__ */

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src/soc/broadcom/cygnus/include/soc/sdram.h
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_SDRAM_H__
#define __SOC_BROADCOM_CYGNUS_SDRAM_H__
#include <stdint.h>
void ddr_init2(void);
void sdram_init(void);
uint32_t sdram_size_mb(void);
#endif /* __SOC_BROADCOM_CYGNUS_SDRAM_H__ */

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src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
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src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
#define __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
#include <soc/cygnus_types.h>
#define GLOBAL_REG_RBUS_START 0x0000000000000000LL
uint32 REGRD(uint32 address);
uint32 REGWR(uint32 address, uint32 data);
#define DDR_PHY_REG_READ(_unit, _pc, flags, _reg_addr, _val) \
(*(uint32 *)_val = REGRD((_pc) + (_reg_addr)))
/* soc_ddr40_phy_reg_ci_read((_unit), (_pc), (_reg_addr), (_val)) */
#define DDR_PHY_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \
REGWR((_pc) + (_reg_addr), (_val))
/* soc_ddr40_phy_reg_ci_write((_unit), (_pc), (_reg_addr), (_val)) */
#define DDR_PHY_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \
REGWR((_pc) + (_reg_addr), (REGRD((_pc) + (_reg_addr)) & ~(_mask)) | ((_val) & (_mask)))
/* soc_ddr40_phy_reg_ci_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) */
#define DDR_PHY_GET_FIELD(m, c, r, f) \
GET_FIELD(m, c, r, f)
#define DDR_PHY_SET_FIELD(m, c, r, f, d) \
SET_FIELD(m, c, r, f, d)
#endif /* __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__ */

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src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
#define __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
#include <delay.h>
#include <soc/cygnus_types.h>
#undef printf
#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
#include <console/console.h>
#define printf(args...) printk(BIOS_INFO, args)
#else
#define printf(args...)
#endif
#ifndef SOC_E_NONE
#define SOC_E_NONE 0x0
#endif
#ifndef SOC_E_FAIL
#define SOC_E_FAIL 0x1
#endif
#ifndef SOC_E_TIMEOUT
#define SOC_E_TIMEOUT 0x2
#endif
#ifndef SOC_E_MEMORY
#define SOC_E_MEMORY 0x4
#endif
#define SET_ADDR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
#define SET_VREF_DAC_CONTROL(v) ((v) & 0xFFFFF)
#define SET_WR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
#define SET_WR_CHAN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x000F7))
#define SET_RD_VDL_FORCE(v) (0x10000 | ((v) & 0x010FF))
#define SET_RD_EN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x001FF))
#define SET_RD_CONTROL(v) ((v) & 0x0001F)
#define SHMOO_AND28_PHY_TYPE_RSVP 0
#define SHMOO_AND28_PHY_TYPE_E0 0xE0
#define SHMOO_AND28_PHY_TYPE_E2 0xE2
#define SHMOO_AND28_PHY_TYPE_F0 0xF0
#define SHMOO_AND28_CTL_TYPE_RSVP 0
#define SHMOO_AND28_CTL_TYPE_RSVP_STR "t0"
#define SHMOO_AND28_CTL_TYPE_1 1
#define SHMOO_AND28_CTL_TYPE_1_STR "t1"
#define SHMOO_AND28_DRAM_TYPE_RSVP 0
#define SHMOO_AND28_DRAM_TYPE_DDR3 3
#define SHMOO_AND28_DRAM_TYPE_DDR3L 31
#define SHMOO_AND28_DRAM_TYPE_DDR4 4
#define SHMOO_AND28_DRAM_TYPE_GDDR5 5
#define SHMOO_AND28_PHY_REG_BASE_RSVP 0
#define SHMOO_AND28_PHY_REG_BASE_CYGNUS 0x18011000
#define SHMOO_AND28_PHY_REG_BASE_GREYHOUND 0x18011000
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_RSVP 0
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_GREYHOUND 0x18010C00
#define SHMOO_AND28_CHIP_ID_RSVP 0
#define SHMOO_AND28_CHIP_ID_CYGNUS 0xC
#define SHMOO_AND28_CHIP_ID_GREYHOUND 0x6
#define SHMOO_AND28_CHIP_ID SHMOO_AND28_CHIP_ID_CYGNUS
#define SHMOO_AND28_PHY_TYPE SHMOO_AND28_PHY_TYPE_E2
#define SHMOO_AND28_PHY_REG_BASE SHMOO_AND28_PHY_REG_BASE_CYGNUS
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE_CYGNUS
#define SHMOO_AND28_CTL_TYPE SHMOO_AND28_CTL_TYPE_1
#define SHMOO_AND28_DRAM_TYPE SHMOO_AND28_DRAM_TYPE_DDR3L
#define SHMOO_AND28_PHY_BITWIDTH 16
#define SHMOO_AND28_PHY_CONSTANT_CONFIG 0
#define PHY_AND28_E2 SHMOO_AND28_PHY_TYPE
#define SHMOO_AND28_PHY_BITWIDTH_IS_32 (SHMOO_AND28_PHY_BITWIDTH >> 5)
#define YDC_DDR_BIST_PHY_BITWIDTH_IS_32 SHMOO_AND28_PHY_BITWIDTH_IS_32
#define YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE
#define SHMOO_AND28_BIT 1
#define SHMOO_AND28_BYTE (SHMOO_AND28_BIT << 3)
#define SHMOO_AND28_HALFWORD (SHMOO_AND28_BYTE << 1)
#define SHMOO_AND28_WORD (SHMOO_AND28_HALFWORD << 1)
#define SHMOO_AND28_DOUBLEWORD (SHMOO_AND28_WORD << 1)
#define SHMOO_AND28_QUADWORD (SHMOO_AND28_DOUBLEWORD << 1)
#define SHMOO_AND28_SHORT_SLEEP 1
#define SHMOO_AND28_LONG_SLEEP 10
#define SHMOO_AND28_DEEP_SLEEP 100
#define SHMOO_AND28_HIBERNATION 1000
#define SHMOO_AND28_STASIS 1000000
#define SHMOO_AND28_SHMOO_RSVP -1
#define SHMOO_AND28_RD_EN 23
#define SHMOO_AND28_RD_EXTENDED 50
#define SHMOO_AND28_WR_EXTENDED 60
#define SHMOO_AND28_ADDR_EXTENDED 71
#define SHMOO_AND28_CTRL_EXTENDED 72
#define SHMOO_AND28_DDR3_SEQUENCE_COUNT 5
#define SHMOO_AND28_DDR3L_SEQUENCE_COUNT 5
/* BEGIN: EXTRA */
/* END: EXTRA */
#define SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED 1
#define SHMOO_AND28_REPEAT 9
#define SHMOO_AND28_REPEAT_HALF (SHMOO_COMBO28_REPEAT >> 1)
#define SHMOO_AND28_SEQUENTIAL 0
#define SHMOO_AND28_SINGLE 1
#define SHMOO_AND28_ACTION_RSVP -1
#define SHMOO_AND28_ACTION_RESTORE 0
#define SHMOO_AND28_ACTION_RUN 1
#define SHMOO_AND28_ACTION_SAVE 2
#define SHMOO_AND28_ACTION_RUN_AND_SAVE 3
#define SHMOO_AND28_MAX_INTERFACES 8
#define SHMOO_AND28_INTERFACE_RSVP -1
#define SHMOO_AND28_BYTES_PER_INTERFACE 4
#define SHMOO_AND28_BIST_NOF_PATTERNS 8
#define SHMOO_AND28_BIST_MPR_NOF_PATTERNS 4
#define SHMOO_AND28_MAX_VISIBLE_UI_COUNT 4
#define SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT 4
#define SHMOO_AND28_LAST_EFFECTIVE_UI (SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT - 1)
#define SHMOO_AND28_MAX_VDL_LENGTH 256
#define SHMOO_AND28_MAX_VREF_RANGE 64
#define SHMOO_AND28_MAX_ZQ_CAL_RANGE 32
#define SHMOO_AND28_RESULT2D_X SHMOO_AND28_MAX_VDL_LENGTH
#define SHMOO_AND28_RESULT2D_Y SHMOO_AND28_MAX_VREF_RANGE
#define SHMOO_AND28_STRING_LENGTH (SHMOO_AND28_RESULT2D_X + 1)
#define SHMOO_AND28_ERROR_ARRAY_LENGTH 4
#define SHMOO_AND28_CALIB_CENTER_PASS 111
#define SHMOO_AND28_CALIB_RISING_EDGE 011
#define SHMOO_AND28_CALIB_FALLING_EDGE 100
#define SHMOO_AND28_CALIB_PASS_START 001
#define SHMOO_AND28_CALIB_FAIL_START 110
#define SHMOO_AND28_CALIB_VDL_ZERO 000
#define SHMOO_AND28_VDL_TFIX 18
#define SHMOO_AND28_RD_DATA_DLY_INIT 7
#define SHMOO_AND28_RD_EN_CYC_INIT 1
#define SHMOO_AND28_RD_EN_VDL_INIT 0
#define SHMOO_AND28_RD_DQ_VDL_INIT 0
#define SHMOO_AND28_RD_DQ_FAIL_CAP 5
#define SHMOO_AND28_RD_DQS_VDL_OFFSET SHMOO_AND28_RD_DQ_VDL_INIT
#define SHMOO_AND28_WR_CYC_INIT 0
#define SHMOO_AND28_PHY_NOF_AD 16
#define SHMOO_AND28_PHY_NOF_BA 3
#define SHMOO_AND28_PHY_NOF_AUX 3
#define SHMOO_AND28_PHY_NOF_CS 2
typedef struct and28_shmoo_dram_info_s {
uint32 ctl_type;
uint32 dram_type;
uint32 dram_bitmap;
uint32 interface_bitwidth;
int num_columns;
int num_rows;
int num_banks;
int data_rate_mbps;
int ref_clk_mhz;
uint32 refi;
uint32 command_parity_latency;
int sim_system_mode;
} and28_shmoo_dram_info_t;
typedef struct and28_shmoo_config_param_s {
uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD];
uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA];
uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX];
uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS];
uint16 control_regs_par;
uint16 control_regs_ras_n;
uint16 control_regs_cas_n;
uint16 control_regs_cke;
uint16 control_regs_rst_n;
uint16 control_regs_odt;
uint16 control_regs_we_n;
uint32 control_regs_vref_dac_control;
uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS];
uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint8 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE];
} and28_shmoo_config_param_t;
typedef struct and28_vendor_info_s {
uint32 dram_density;
uint32 fifo_depth;
uint32 revision_id;
uint32 manufacture_id;
} and28_vendor_info_t;
typedef struct and28_shmoo_container_s {
uint32 sizeX;
uint32 sizeY;
uint32 yCapMin;
uint32 yCapMax;
uint32 yJump;
uint32 calibMode;
uint32 calibPos;
uint32 calibStart;
uint32 result2D[(SHMOO_AND28_RESULT2D_X)*(SHMOO_AND28_RESULT2D_Y)];
uint32 resultData[SHMOO_AND28_WORD];
uint32 shmooType;
uint32 dramType;
uint32 ctlType;
uint32 trefi;
uint32 step1000;
uint32 size1000UI;
uint32 endUI[SHMOO_AND28_MAX_VISIBLE_UI_COUNT];
uint32 engageUIshift;
uint32 wckInv;
} and28_shmoo_container_t;
typedef struct and28_step_size_s {
uint32 step1000;
uint32 size1000UI;
} and28_step_size_t;
typedef struct and28_ui_position_s {
uint32 ui;
uint32 position;
} and28_ui_position_t;
typedef uint32 and28_shmoo_error_array_t[SHMOO_AND28_ERROR_ARRAY_LENGTH];
int soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi);
int soc_and28_shmoo_phy_init(int unit, int phy_ndx);
int soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat,
int plot, int action, and28_shmoo_config_param_t *config_param);
#endif /* __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__ */

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src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h
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src/soc/broadcom/cygnus/include/soc/tz.h
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_TZ_H__
#define __SOC_BROADCOM_CYGNUS_TZ_H__
#include <stdint.h>
#define TZ_STATE_SECURE 0
#define TZ_STATE_NON_SECURE 1
/*
* Masters (for parameter masters in "tz_set_masters_security")
*/
#define CYGNUS_M_Pcie0_m0 0x00000003
#define CYGNUS_M_Pcie1_m0 0x0000000c
#define CYGNUS_M_cmicd_m0 0x00000030
#define CYGNUS_M_ext_m0 0x000000c0
#define CYGNUS_M_ext_m1 (0x00000003 << 8)
#define CYGNUS_M_sdio_m0 (0x0000000c << 8)
#define CYGNUS_M_sdio_m1 (0x00000030 << 8)
#define CYGNUS_M_amac_m0 (0x000000c0 << 8)
#define CYGNUS_M_amac_m1 (0x00000003 << 16)
#define CYGNUS_M_usb2h_m0 (0x0000000c << 16)
#define CYGNUS_M_usb2d_m0 (0x00000030 << 16)
#define CYGNUS_M_a9jtag_m0 (0x000000c0 << 16)
/*
* Non virtual slaves (for parameter slave_vector in "tz_set_non_virtual_slaves_security")
* Note: the order has to match the order in non_virtual_slave_regs[] array from tz.c
*/
#define CYGNUS_S_Ihost_acp (0x1 << 0)
#define CYGNUS_S_PCIe0_s0 (0x1 << 1)
#define CYGNUS_S_PCIe1_s0 (0x1 << 2)
#define CYGNUS_S_ihost_s0 (0x1 << 3)
#define CYGNUS_S_A9jtag_s0 (0x1 << 4)
#define CYGNUS_S_CMICd_s0 (0x1 << 5)
#define CYGNUS_S_mhost0_s0 (0x1 << 6)
#define CYGNUS_S_mhost1_s0 (0x1 << 7)
#define CYGNUS_S_Crypto_s0 (0x1 << 8)
#define CYGNUS_S_DMU_s0 (0x1 << 9)
/*
* Peripherals (for parameter slave_vector in "tz_set_periph_security")
*/
#define CYGNUS_periph_APBx_DMU 0x00008000
#define CYGNUS_periph_APBx_cru 0x00004000
#define CYGNUS_periph_APBx_ccg_smbus1 0x00000800
#define CYGNUS_periph_APBx_ccg_gpio 0x00000400
#define CYGNUS_periph_APBx_ccg_watchdog 0x00000200
#define CYGNUS_periph_APBx_ccg_smbus0 0x00000100
#define CYGNUS_periph_APBx_ccg_srab 0x00000080
#define CYGNUS_periph_APBx_ccg_timer3 0x00000040
#define CYGNUS_periph_APBx_ccg_timer2 0x00000020
#define CYGNUS_periph_APBx_ccg_timer1 0x00000010
#define CYGNUS_periph_APBx_ccg_timer0 0x00000008
#define CYGNUS_periph_APBx_ccg_mdio 0x00000004
#define CYGNUS_periph_APBx_ccg_pwm 0x00000002
#define CYGNUS_periph_APBx_icfg 0x00000001
#define CYGNUS_periph_APBy_ccg_spi5 (0x00002000 << 16)
#define CYGNUS_periph_APBy_ccg_spi4 (0x00001000 << 16)
#define CYGNUS_periph_APBy_ccg_spi3 (0x00000800 << 16)
#define CYGNUS_periph_APBy_ccg_spi2 (0x00000400 << 16)
#define CYGNUS_periph_APBy_ccg_spi1 (0x00000200 << 16)
#define CYGNUS_periph_APBy_ccg_spi0 (0x00000100 << 16)
#define CYGNUS_periph_APBy_ccg_uart4 (0x00000010 << 16)
#define CYGNUS_periph_APBy_ccg_uart3 (0x00000008 << 16)
#define CYGNUS_periph_APBy_ccg_uart2 (0x00000004 << 16)
#define CYGNUS_periph_APBy_ccg_uart1 (0x00000002 << 16)
#define CYGNUS_periph_APBy_ccg_uart0 (0x00000001 << 16)
/*
* Sececure Peripherals (for parameter slave_vector in "tz_set_sec_periphs_security")
*/
#define CYGNUS_sec_periph_APBz_sotp 0x00000020
#define CYGNUS_sec_periph_APBz_tzpc 0x00000010
#define CYGNUS_sec_periph_APBz_ccg_wdog 0x00000008
#define CYGNUS_sec_periph_APBz_ccs_rng 0x00000004
#define CYGNUS_sec_periph_APBz_ccs_pka 0x00000002
#define CYGNUS_sec_periph_APBz_ccs_gpio 0x00000001
/*
* Cfg Slaves (for parameter slave_vector in "tz_set_cfg_slaves_security")
*/
#define CYGNUS_cfg_slv_APBr_mhost0 0x00004000
#define CYGNUS_cfg_slv_APBr_dma_s1 0x00000200
#define CYGNUS_cfg_slv_APBr_dma_s0 0x00000100
#define CYGNUS_cfg_slv_APBr_acpal 0x00000040
#define CYGNUS_cfg_slv_APBr_smau 0x00000020
#define CYGNUS_cfg_slv_APBr_pcie1 0x00000008
#define CYGNUS_cfg_slv_APBr_pcie0 0x00000004
#define CYGNUS_cfg_slv_APBr_ddr 0x00000001
#define CYGNUS_cfg_slv_APBs_sram (0x00004000 << 16)
#define CYGNUS_cfg_slv_APBs_usb2d (0x00001000 << 16)
#define CYGNUS_cfg_slv_APBs_amac1 (0x00000400 << 16)
#define CYGNUS_cfg_slv_APBs_usb2h_apb2 (0x00000200 << 16)
#define CYGNUS_cfg_slv_APBs_usb2h_apb1 (0x00000100 << 16)
#define CYGNUS_cfg_slv_APBs_qspi (0x00000080 << 16)
#define CYGNUS_cfg_slv_APBs_nand (0x00000040 << 16)
#define CYGNUS_cfg_slv_APBs_nor (0x00000020 << 16)
#define CYGNUS_cfg_slv_APBs_sdio1 (0x00000008 << 16)
#define CYGNUS_cfg_slv_APBs_amac0 (0x00000004 << 16)
#define CYGNUS_cfg_slv_APBs_sdio0 (0x00000002 << 16)
/*
* Wrapper1 (for parameter wrapper1 in "tz_set_wrapper_security")
*/
#define CYGNUS_APB_W1_wrp_master_ihost_m0 0x00000001
#define CYGNUS_APB_W1_wrp_master_pcie0_m0 0x00000002
#define CYGNUS_APB_W1_wrp_master_pcie1_m0 0x00000004
#define CYGNUS_APB_W1_wrp_master_cmicd_m0 0x00000008
#define CYGNUS_APB_W1_wrp_master_mhost0_m0 0x00000010
#define CYGNUS_APB_W1_wrp_master_mhost1_m0 0x00000020
#define CYGNUS_APB_W1_wrp_slave_ihost_acp 0x00000040
#define CYGNUS_APB_W1_wrp_slave_ihost_s0 0x00000080
#define CYGNUS_APB_W1_wrp_slave_pcie0_s0 0x00000100
#define CYGNUS_APB_W1_wrp_slave_pcie1_s0 0x00000200
#define CYGNUS_APB_W1_wrp_slave_cmicd_s0 0x00000400
#define CYGNUS_APB_W1_wrp_slave_smau_s0 0x00000800
#define CYGNUS_APB_W1_wrp_slave_mhost0_s0 0x00001000
#define CYGNUS_APB_W1_wrp_slave_mhost1_s0 0x00002000
#define CYGNUS_APB_W1_wrp_slave_apbr 0x00004000
#define CYGNUS_APB_W1_wrp_master_dma_m0 0x00008000
/*
* Wrapper2 (for parameter wrapper2 in "tz_set_wrapper_security")
*/
#define CYGNUS_APB_W2_wrp_ds_ds_2 0x00000008
#define CYGNUS_APB_W2_sdrom 0x00000004
#define CYGNUS_APB_W2_wrp_ds_ds_1 0x00000002
#define CYGNUS_APB_W2_wrp_ds_ds_0 0x00000001
/*
* Wrapper3 (for parameter wrapper3 in "tz_set_wrapper_security")
*/
#define CYGNUS_APB_W3_wrp_master_amac_m1 0x00002000
#define CYGNUS_APB_W3_wrp_ds_ds_3 0x00001000
#define CYGNUS_APB_W3_wrp_slave_apbs 0x00000800
#define CYGNUS_APB_W3_wrp_slave_sram_s0 0x00000400
#define CYGNUS_APB_W3_wrp_master_sdio_m1 0x00000200
#define CYGNUS_APB_W3_wrp_slave_a9jtag_s0 0x00000100
#define CYGNUS_APB_W3_wrp_slave_crypto_s0 0x00000080
#define CYGNUS_APB_W3_wrp_master_usb2h_m0 0x00000040
#define CYGNUS_APB_W3_wrp_master_a9jtag_m0 0x00000020
#define CYGNUS_APB_W3_wrp_master_ext_m1 0x00000010
#define CYGNUS_APB_W3_wrp_master_sdio_m0 0x00000008
#define CYGNUS_APB_W3_wrp_master_ext_m0 0x00000004
#define CYGNUS_APB_W3_wrp_master_usb2d_m0 0x00000002
#define CYGNUS_APB_W3_wrp_master_amac_m0 0x00000001
/*
* Wrapper4 (for parameter wrapper4 in "tz_set_wrapper_security")
*/
#define CYGNUS_APB_W4_wrp_slave_ext_s1 0x00000040
#define CYGNUS_APB_W4_wrp_slave_dmu_s0 0x00000020
#define CYGNUS_APB_W4_wrp_slave_ext_s0 0x00000010
#define CYGNUS_APB_W4_wrp_master_dmu_m0 0x00000008
#define CYGNUS_APB_W4_wrp_slave_apbz 0x00000004
#define CYGNUS_APB_W4_wrp_slave_apby 0x00000002
#define CYGNUS_APB_W4_wrp_slave_apbx 0x00000001
/*
* Ext Slaves (for parameter slave_vector in "tz_set_ext_slaves_security")
*/
#define CYGNUS_AXIIC_ext_s0_slave_0 0x00000001 /* LCD */
#define CYGNUS_AXIIC_ext_s0_slave_1 0x00000002 /* Camera */
#define CYGNUS_AXIIC_ext_s0_slave_2 0x00000004
#define CYGNUS_AXIIC_ext_s0_slave_3 0x00000008 /* Smartcard */
#define CYGNUS_AXIIC_ext_s0_slave_4 0x00000010 /* S-GPIO */
#define CYGNUS_AXIIC_ext_s0_slave_5 0x00000020 /* GPIO */
#define CYGNUS_AXIIC_ext_s0_slave_6 0x00000040 /* ADC_APB */
#define CYGNUS_AXIIC_ext_s0_slave_7 0x00000080
#define CYGNUS_AXIIC_ext_s0_slave_8 0x00000100 /* GFX_S0 */
#define CYGNUS_AXIIC_ext_s0_slave_9 0x00000200 /* MIPI */
#define CYGNUS_AXIIC_ext_s0_slave_10 0x00000400 /* ASIU_TOP */
#define CYGNUS_AXIIC_ext_s0_slave_11 0x00000800 /* D1W */
#define CYGNUS_AXIIC_ext_s0_slave_12 0x00001000 /* Keypad */
#define CYGNUS_AXIIC_ext_s0_slave_13 0x00002000 /* Keypad */
#define CYGNUS_AXIIC_ext_s0_slave_14 0x00004000 /* Audio */
#define CYGNUS_AXIIC_ext_s0_slave_15 0x00008000
#define CYGNUS_AXIIC_ext_s1_slave_0 (0x00000001 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_1 (0x00000002 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_2 (0x00000004 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_3 (0x00000008 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_4 (0x00000010 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_5 (0x00000020 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_6 (0x00000040 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_7 (0x00000080 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_8 (0x00000100 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_9 (0x00000200 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_10 (0x00000400 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_11 (0x00000800 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_12 (0x00001000 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_13 (0x00002000 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_14 (0x00004000 << 16)
#define CYGNUS_AXIIC_ext_s1_slave_15 (0x00008000 << 16)
void tz_set_masters_security(uint32_t masters, uint32_t ns_bit);
void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2,
uint32_t wrapper3, uint32_t wrapper4,
uint32_t ns_bit);
void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit);
void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit);
void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
void tz_set_sram_sec_region(uint32_t r0size);
void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
#endif

302
src/soc/broadcom/cygnus/iomux.c
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@ -1,302 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <gpio.h>
#include <stdlib.h>
#include <string.h>
#include <soc/addressmap.h>
#define CYGNUS_NUM_IOMUX_REGS 8
#define CYGNUS_NUM_MUX_PER_REG 8
#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
CYGNUS_NUM_MUX_PER_REG)
/*
* Cygnus IOMUX pinctrl core
*
* @base1: second I/O register base
*/
struct cygnus_pinctrl {
void *base1;
};
static struct cygnus_pinctrl pinctrl_data = {
.base1 = (void *)IPROC_IOMUX_OVERRIDE_BASE
};
/*
* Certain pins can be individually muxed to GPIO function
*
* @is_supported: flag to indicate GPIO mux is supported for this pin
* @offset: register offset for GPIO mux override of a pin
* @shift: bit shift for GPIO mux override of a pin
*/
struct cygnus_gpio_mux {
int is_supported;
unsigned int offset;
unsigned int shift;
};
/*
* Description of a pin in Cygnus
*
* @pin: pin number
* @name: pin name
* @gpio_mux: GPIO override related information
*/
struct cygnus_pin {
unsigned pin;
const char *name;
struct cygnus_gpio_mux gpio_mux;
};
#define CYGNUS_PIN_DESC(p, n, i, o, s) \
{ \
.pin = p, \
.name = n, \
.gpio_mux = { \
.is_supported = i, \
.offset = o, \
.shift = s, \
}, \
}
/*
* List of pins in Cygnus
*/
static struct cygnus_pin cygnus_pins[] = {
CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
};
int cygnus_gpio_request_enable(void *priv, unsigned pin)
{
struct cygnus_pinctrl *pinctrl = (struct cygnus_pinctrl *)priv;
struct cygnus_gpio_mux *mux = &cygnus_pins[pin].gpio_mux;
u32 val;
/* not all pins support GPIO pinmux override */
if (!mux->is_supported)
return -ENOTSUPP;
val = read32(pinctrl->base1 + mux->offset);
val |= 0x3 << mux->shift;
write32(pinctrl->base1 + mux->offset, val);
printk(BIOS_INFO, "gpio request enable pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
return 0;
}
void cygnus_gpio_disable_free(void *priv, unsigned pin)
{
struct cygnus_pinctrl *pinctrl = (struct cygnus_pinctrl *)priv;
struct cygnus_gpio_mux *mux = &cygnus_pins[pin].gpio_mux;
u32 val;
if (!mux->is_supported)
return;
val = read32(pinctrl->base1 + mux->offset);
val &= ~(0x3 << mux->shift);
write32(pinctrl->base1 + mux->offset, val);
printk(BIOS_INFO, "gpio disable free pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
}
void *cygnus_pinmux_init()
{
return &pinctrl_data;
}

128
src/soc/broadcom/cygnus/ns16550.c
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@ -1,128 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
* Copyright (C) Broadcom Corporation
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <delay.h>
#include <soc/ns16550.h>
#define SYS_NS16550_CLK 100000000
#define SYS_NS16550_BAUDRATE 115200
#define MODE_X_DIV 16
#define SINGLE_CHAR_TIMEOUT (50 * 1000)
static struct ns16550 * const regs =
(void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
static int calc_divisor(void)
{
/* Compute divisor value. Normally, we should simply return:
* ns16550_clk / MODE_X_DIV / baudrate
* but we need to round that value by adding 0.5.
* Rounding is especially important at high baud rates.
*/
int div = MODE_X_DIV * SYS_NS16550_BAUDRATE;
return (SYS_NS16550_CLK + div / 2) / div;
}
static void ns16550_init(void)
{
int baud_divisor = calc_divisor();
while (!(read32(&regs->lsr) & UART_LSR_TEMT))
;
write32(&regs->ier, 0);
write32(&regs->lcr, UART_LCR_BKSE | UART_LCR_8N1);
write32(&regs->dll, 0);
write32(&regs->dlm, 0);
write32(&regs->lcr, UART_LCR_8N1);
write32(&regs->mcr, UART_MCR_DTR | UART_MCR_RTS);
/* clear & enable FIFOs */
write32(&regs->fcr, UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
write32(&regs->lcr, UART_LCR_BKSE | UART_LCR_8N1);
write32(&regs->dll, baud_divisor & 0xff);
write32(&regs->dlm, (baud_divisor >> 8) & 0xff);
write32(&regs->lcr, UART_LCR_8N1);
}
static void ns16550_tx_byte(unsigned char data)
{
while ((read32(&regs->lsr) & UART_LSR_THRE) == 0)
;
write32(&regs->thr, data);
}
static void ns16550_tx_flush(void)
{
while (!(read32(&regs->lsr) & UART_LSR_TEMT))
;
}
static int ns16550_tst_byte(void)
{
return (read32(&regs->lsr) & UART_LSR_DR) != 0;
}
static unsigned char ns16550_rx_byte(void)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i && !ns16550_tst_byte()) {
udelay(1);
i--;
}
if (i)
return read32(&regs->rbr);
else
return 0x0;
}
void uart_init(int idx)
{
ns16550_init();
}
void uart_tx_byte(int idx, unsigned char data)
{
ns16550_tx_byte(data);
}
void uart_tx_flush(int idx)
{
ns16550_tx_flush();
}
unsigned char uart_rx_byte(int idx)
{
return ns16550_rx_byte();
}
#ifndef __PRE_RAM__
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = (uintptr_t)regs;
serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
#endif

31
src/soc/broadcom/cygnus/phy_reg_access.c
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@ -1,31 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "soc/shmoo_and28/phy_reg_access.h"
uint32 REGRD (uint32 address) {
volatile unsigned long data;
data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));
//printf("REGRD %08X=%08X\n", address, data);
return data;
}
uint32 REGWR (uint32 address, uint32 data) {
((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
//printf("REGWR %08X=%08X\n", address, data);
// return SOC_E_NONE;
return 0;
}

52
src/soc/broadcom/cygnus/romstage.c
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@ -1,52 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/stages.h>
#include <armv7.h>
#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
#include <soc/gpio.h>
#include <soc/sdram.h>
#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
void main(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init();
timestamp_add_now(TS_AFTER_INITRAM);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
gpio_init();
cbmem_initialize_empty();
run_ramstage();
}

63
src/soc/broadcom/cygnus/sdram.c
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <symbols.h>
#include <soc/sdram.h>
#define DRAM_TEST_LEN 0x8000000
static void test_ddr(void)
{
if (IS_ENABLED(CONFIG_CYGNUS_SDRAM_TEST_DDR)) {
uint32_t *test_buffer = (uint32_t *) _dram;
uint32_t len = DRAM_TEST_LEN;
uint32_t i;
uint32_t fail_count = 0;
printk(BIOS_INFO, "test ddr start from 0x%p to 0x%p\n", test_buffer,
test_buffer + len);
for (i = 0; i < len; i++)
*(test_buffer + i) = i;
for (i = 0; i < len; i++) {
int val = *(test_buffer + i);
if ((i % 0x10000) == 0)
printk(BIOS_INFO, "#");
if (i != val) {
printk(BIOS_ERR, "\ntest_ddr: @ 0x%p: %d != %d\n",
test_buffer + i, i, val);
fail_count++;
}
}
printk(BIOS_INFO, "\ntest ddr end: fail=%d\n", fail_count);
}
}
void sdram_init(void)
{
printk(BIOS_INFO, "sdram initialization is in progress...\n");
ddr_init2();
printk(BIOS_INFO, "sdram initialization is completed.\n");
test_ddr();
}
uint32_t sdram_size_mb(void)
{
return CONFIG_DRAM_SIZE_MB;
}

4884
src/soc/broadcom/cygnus/shmoo_and28.c
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49
src/soc/broadcom/cygnus/soc.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <soc/cygnus.h>
#include <soc/sdram.h>
#include <stddef.h>
#include <stdlib.h>
#include <symbols.h>
static void soc_init(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
usb_init();
}
static void soc_noop(struct device *dev)
{
}
static struct device_operations soc_ops = {
.read_resources = soc_noop,
.set_resources = soc_noop,
.enable_resources = soc_noop,
.init = soc_init,
.scan_bus = 0,
};
static void enable_cygnus_dev(struct device *dev)
{
dev->ops = &soc_ops;
}
struct chip_operations soc_broadcom_cygnus_ops = {
CHIP_NAME("SOC Broadcom Cygnus")
.enable_dev = enable_cygnus_dev,
};

327
src/soc/broadcom/cygnus/spi.c
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@ -1,327 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <timer.h>
#include <delay.h>
#include <stdlib.h>
#include <spi-generic.h>
#include <spi_flash.h>
#include <soc/addressmap.h>
#define IPROC_QSPI_CLK 100000000
/* SPI mode flags */
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
#define SPI_MODE_0 (0|0) /* original MicroWire */
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define QSPI_MAX_HZ 50000000
#define QSPI_MODE SPI_MODE_3
#define QSPI_WAIT_TIMEOUT 200U /* msec */
/* Controller attributes */
#define SPBR_MIN 8U
#define SPBR_MAX 255U
#define NUM_TXRAM 32
#define NUM_RXRAM 32
#define NUM_CDRAM 16
/*
* Register fields
*/
#define MSPI_SPCR0_MSB_BITS_8 0x00000020
/* BSPI registers */
#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
#define BSPI_BUSY_STATUS_REG 0x00c
/* MSPI registers */
#define MSPI_SPCR0_LSB_REG 0x200
#define MSPI_SPCR0_MSB_REG 0x204
#define MSPI_SPCR1_LSB_REG 0x208
#define MSPI_SPCR1_MSB_REG 0x20c
#define MSPI_NEWQP_REG 0x210
#define MSPI_ENDQP_REG 0x214
#define MSPI_SPCR2_REG 0x218
#define MSPI_STATUS_REG 0x220
#define MSPI_CPTQP_REG 0x224
#define MSPI_TXRAM_REG 0x240
#define MSPI_RXRAM_REG 0x2c0
#define MSPI_CDRAM_REG 0x340
#define MSPI_WRITE_LOCK_REG 0x380
#define MSPI_DISABLE_FLUSH_GEN_REG 0x384
/*
* Register access macros
*/
#define REG_RD(x) read32(x)
#define REG_WR(x, y) write32((x), (y))
#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y))
#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y))
/* QSPI private data */
struct qspi_priv {
/* Specified SPI parameters */
unsigned int max_hz;
unsigned int spi_mode;
int mspi_enabled;
int mspi_16bit;
int bus_claimed;
/* Registers */
void *reg;
};
static struct qspi_priv qspi_slave;
static struct qspi_priv *to_qspi_slave(const struct spi_slave *slave)
{
return &qspi_slave;
}
static int mspi_enable(struct qspi_priv *priv)
{
struct stopwatch sw;
/* Switch to MSPI if not yet */
if ((REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
while (!stopwatch_expired(&sw)) {
if ((REG_RD(priv->reg + BSPI_BUSY_STATUS_REG) & 1)
== 0) {
REG_WR(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG,
1);
udelay(1);
break;
}
udelay(1);
}
if (REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) != 1)
return -1;
}
priv->mspi_enabled = 1;
return 0;
}
static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
{
struct qspi_priv *priv = to_qspi_slave(slave);
if (priv->bus_claimed)
return -1;
if (!priv->mspi_enabled)
if (mspi_enable(priv))
return -1;
/* MSPI: Enable write lock */
REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 1);
priv->bus_claimed = 1;
return 0;
}
static void spi_ctrlr_release_bus(const struct spi_slave *slave)
{
struct qspi_priv *priv = to_qspi_slave(slave);
/* MSPI: Disable write lock */
REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 0);
priv->bus_claimed = 0;
}
#define RXRAM_16B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + ((i) << 2)) & 0xff)
#define RXRAM_8B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + \
((((i) << 1) + 1) << 2)) & 0xff)
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
size_t bytesout, void *din, size_t bytesin)
{
struct qspi_priv *priv = to_qspi_slave(slave);
const u8 *tx = (const u8 *)dout;
u8 *rx = (u8 *)din;
unsigned int bytes = bytesout + bytesin;
unsigned int rx_idx = 0;
unsigned int tx_idx = 0;
unsigned int in = 0;
unsigned int chunk;
unsigned int queues;
unsigned int i;
struct stopwatch sw;
if (!priv->bus_claimed)
return -1;
if (bytes & 1) {
/* Use 8-bit queue for odd-bytes transfer */
if (priv->mspi_16bit) {
REG_SET(priv->reg + MSPI_SPCR0_MSB_REG,
MSPI_SPCR0_MSB_BITS_8);
priv->mspi_16bit = 0;
}
} else {
/* Use 16-bit queue for even-bytes transfer */
if (!priv->mspi_16bit) {
REG_CLR(priv->reg + MSPI_SPCR0_MSB_REG,
MSPI_SPCR0_MSB_BITS_8);
priv->mspi_16bit = 1;
}
}
while (bytes) {
/* Separate code for 16bit and 8bit transfers for performance */
if (priv->mspi_16bit) {
/* Determine how many bytes to process this time */
chunk = min(bytes, NUM_CDRAM * 2);
queues = (chunk - 1) / 2 + 1;
bytes -= chunk;
/* Fill CDRAMs */
for (i = 0; i < queues; i++)
REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
0xc2);
/* Fill TXRAMs */
for (i = 0; i < chunk; i++) {
REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 2),
(tx && (tx_idx < bytesout)) ?
tx[tx_idx] : 0xff);
tx_idx++;
}
} else {
/* Determine how many bytes to process this time */
chunk = min(bytes, NUM_CDRAM);
queues = chunk;
bytes -= chunk;
/* Fill CDRAMs and TXRAMS */
for (i = 0; i < chunk; i++) {
REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
0x82);
REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 3),
(tx && (tx_idx < bytesout)) ?
tx[tx_idx] : 0xff);
tx_idx++;
}
}
/* Setup queue pointers */
REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
REG_WR(priv->reg + MSPI_ENDQP_REG, queues - 1);
/* Deassert CS */
if (bytes == 0)
REG_CLR(priv->reg + MSPI_CDRAM_REG +
((queues - 1) << 2), 0x0);
/* Kick off */
REG_WR(priv->reg + MSPI_STATUS_REG, 0);
REG_WR(priv->reg + MSPI_SPCR2_REG, 0xc0); /* cont | spe */
/* Wait for completion */
stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
while (!stopwatch_expired(&sw)) {
if (REG_RD(priv->reg + MSPI_STATUS_REG) & 1)
break;
}
if ((REG_RD(priv->reg + MSPI_STATUS_REG) & 1) == 0) {
/* Make sure no operation is in progress */
REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
udelay(1);
return -1;
}
/* Read data */
if (rx) {
if (priv->mspi_16bit) {
for (i = 0; i < chunk; i++) {
if (rx_idx >= bytesout) {
rx[in] = RXRAM_16B(priv, i);
in++;
}
rx_idx++;
}
} else {
for (i = 0; i < chunk; i++) {
if (rx_idx >= bytesout) {
rx[in] = RXRAM_8B(priv, i);
in++;
}
rx_idx++;
}
}
}
}
return 0;
}
static int spi_ctrlr_setup(const struct spi_slave *slave)
{
struct qspi_priv *priv = &qspi_slave;
unsigned int spbr;
priv->max_hz = QSPI_MAX_HZ;
priv->spi_mode = QSPI_MODE;
priv->reg = (void *)(IPROC_QSPI_BASE);
priv->mspi_enabled = 0;
priv->bus_claimed = 0;
/* MSPI: Basic hardware initialization */
REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0);
REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0);
REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
REG_WR(priv->reg + MSPI_ENDQP_REG, 0);
REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
/* MSPI: SCK configuration */
spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1;
REG_WR(priv->reg + MSPI_SPCR0_LSB_REG,
MAX(MIN(spbr, SPBR_MAX), SPBR_MIN));
/* MSPI: Mode configuration (8 bits by default) */
priv->mspi_16bit = 0;
REG_WR(priv->reg + MSPI_SPCR0_MSB_REG,
0x80 | /* Master */
(8 << 2) | /* 8 bits per word */
(priv->spi_mode & 3)); /* mode: CPOL / CPHA */
return 0;
}
static const struct spi_ctrlr spi_ctrlr = {
.setup = spi_ctrlr_setup,
.claim_bus = spi_ctrlr_claim_bus,
.release_bus = spi_ctrlr_release_bus,
.xfer = spi_ctrlr_xfer,
.max_xfer_size = 65535,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{
.ctrlr = &spi_ctrlr,
.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
},
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

67
src/soc/broadcom/cygnus/timer.c
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <timer.h>
#define TIMER_GLB_TIM_CTRL_PRESC_MASK 0x0000FF00
#define TIMER_GLB_TIM_CTRL_TIM_EN 0x00000001
#define TIMER_GLB_TIM_CTRL_PRESC 0x0
/*
* arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec.
* arm clk is set by the bootrom. See util/broadcom/unauth.cfg for details.
*/
#define PERIPH_CLOCK 500
#define CLOCKS_PER_USEC (PERIPH_CLOCK / \
(((TIMER_GLB_TIM_CTRL_PRESC & TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1))
struct cygnus_timer {
u32 gtim_glob_low;
u32 gtim_glob_hi;
u32 gtim_glob_ctrl;
};
static struct cygnus_timer * const timer_ptr =
(void *)IPROC_PERIPH_GLB_TIM_REG_BASE;
static inline uint64_t timer_raw_value(void)
{
uint64_t cur_tick;
uint32_t count_h;
uint32_t count_l;
do {
count_h = read32(&timer_ptr->gtim_glob_hi);
count_l = read32(&timer_ptr->gtim_glob_low);
cur_tick = read32(&timer_ptr->gtim_glob_hi);
} while (cur_tick != count_h);
return (cur_tick << 32) + count_l;
}
void timer_monotonic_get(struct mono_time *mt)
{
mono_time_set_usecs(mt, timer_raw_value() / CLOCKS_PER_USEC);
}
void init_timer(void)
{
write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_PRESC);
write32(&timer_ptr->gtim_glob_low, 0);
write32(&timer_ptr->gtim_glob_hi, 0);
write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_TIM_EN);
}

283
src/soc/broadcom/cygnus/tz.c
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/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <soc/tz.h>
#define TZPC_TZPCR0SIZE 0x18034000
#define TZPC_TZPCR0SIZE_MASK 0x000003ff
#define TZPC_TZPCDECPROT0SET 0x18034804
#define TZPC_TZPCDECPROT0CLR 0x18034808
#define TZPC_TZPCDECPROT1SET 0x18034810
#define TZPC_TZPCDECPROT1CLR 0x18034814
#define TZPC_TZPCDECPROT2SET 0x1803481c
#define TZPC_TZPCDECPROT2CLR 0x18034820
#define TZPCDECPROT0_MASK 0x000000FF
#define TZPCDECPROT1_MASK 0x000000FF
#define TZPCDECPROT2_MASK 0x000000FF
#define AXIIC_Ihost_acp_security 0x1a000008
#define AXIIC_PCIe0_s0_security 0x1a000010
#define AXIIC_PCIe1_s0_security 0x1a000014
#define AXIIC_APBY_s0_security 0x1a00002c
#define AXIIC_APBZ_s0_security 0x1a000030
#define AXIIC_APBX_s0_security 0x1a000034
#define AXIIC_ihost_s0_security 0x1a000038
#define AXIIC_A9jtag_s0_security 0x1a00003c
#define AXIIC_APB_W1_security 0x1a000040
#define AXIIC_APB_W2_security 0x1a000044
#define AXIIC_APB_W3_security 0x1a000048
#define AXIIC_APB_W4_security 0x1a00004c
#define AXIIC_APBR_s0_security 0x1a00006c
#define AXIIC_APBS_s0_security 0x1a000070
#define AXIIC_CMICd_s0_security 0x1a000074
#define AXIIC_mhost0_s0_security 0x1a000078
#define AXIIC_mhost1_s0_security 0x1a00007c
#define AXIIC_Crypto_s0_security 0x1a000080
#define AXIIC_DMU_s0_security 0x1a000084
#define AXIIC_ext_s0_security 0x1a000088
#define AXIIC_ext_s1_security 0x1a00008c
#define AXIIC_APBY_s0_security_MASK 0x00003f1f
#define AXIIC_APBZ_s0_security_MASK 0x0000003f
#define AXIIC_APBX_s0_security_MASK 0x0000cfff
#define AXIIC_ext_s0_security_MASK 0xffffffff
#define AXIIC_ext_s1_security_MASK 0xffffffff
#define AXIIC_APBR_s0_security_MASK 0x0000436d
#define AXIIC_APBS_s0_security_MASK 0x000057ee
#define AXIIC_APB_W1_security_MASK 0x0000ffff
#define AXIIC_APB_W2_security_MASK 0x0000000f
#define AXIIC_APB_W3_security_MASK 0x00003fff
#define AXIIC_APB_W4_security_MASK 0x0000007f
/*
* Note: the order need to match corresponding definitions for
* non virtual slave slave_vector in tz.h
*/
static uint32_t non_virtual_slave_regs[] = {
AXIIC_Ihost_acp_security,
AXIIC_PCIe0_s0_security,
AXIIC_PCIe1_s0_security,
AXIIC_ihost_s0_security,
AXIIC_A9jtag_s0_security,
AXIIC_CMICd_s0_security,
AXIIC_mhost0_s0_security,
AXIIC_mhost1_s0_security,
AXIIC_Crypto_s0_security,
AXIIC_DMU_s0_security
};
/*
* Set master security.
* Use defines in tz.h for both parameters.
*/
void tz_set_masters_security(uint32_t masters, uint32_t ns_bit)
{
uint32_t val;
/* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */
if (masters & TZPCDECPROT0_MASK) {
val = masters & TZPCDECPROT0_MASK;
if (ns_bit)
write32((void *)TZPC_TZPCDECPROT0SET, val);
else
write32((void *)TZPC_TZPCDECPROT0CLR, val);
}
/* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */
if ((masters >> 8) & TZPCDECPROT1_MASK) {
val = (masters >> 8) & TZPCDECPROT1_MASK;
if (ns_bit)
write32((void *)TZPC_TZPCDECPROT1SET, val);
else
write32((void *)TZPC_TZPCDECPROT1CLR, val);
}
/* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */
if ((masters >> 16) & TZPCDECPROT2_MASK) {
val = (masters >> 16) & TZPCDECPROT2_MASK;
if (ns_bit)
write32((void *)TZPC_TZPCDECPROT2SET, val);
else
write32((void *)TZPC_TZPCDECPROT2CLR, val);
}
}
/*
* Set non virtual slave security.
* Use defines in tz.h for both parameters.
*/
void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
{
uint32_t i;
uint32_t total = sizeof(non_virtual_slave_regs) /
sizeof(non_virtual_slave_regs[0]);
uint32_t mask = ~(0xffffffff << total);
ns_bit &= 0x1;
slave_vector = slave_vector & mask;
for (i = 0; i < total; i++) {
if (slave_vector & (0x1 << i))
write32((void *)(non_virtual_slave_regs[i]), ns_bit);
}
}
/*
* Set peripheral security.
* Use defines in tz.h for both parameters.
*/
void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit)
{
uint32_t val;
uint32_t mask_x = AXIIC_APBX_s0_security_MASK;
uint32_t mask_y = AXIIC_APBY_s0_security_MASK;
uint32_t tz_periphs_sec_status =
(mask_x & read32((void *)AXIIC_APBX_s0_security)) |
((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_periphs_sec_status &= ~slave_vector;
else
tz_periphs_sec_status |= slave_vector;
val = tz_periphs_sec_status & mask_x;
write32((void *)AXIIC_APBX_s0_security, val);
val = (tz_periphs_sec_status >> 16) & mask_y;
write32((void *)AXIIC_APBY_s0_security, val);
}
/*
* Set sec peripheral security.
* Use defines in tz.h for both parameters.
*/
void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit)
{
uint32_t val;
uint32_t mask = AXIIC_APBZ_s0_security_MASK;
uint32_t tz_sec_periphs_sec_status =
read32((void *)AXIIC_APBZ_s0_security);
if (ns_bit == TZ_STATE_SECURE)
tz_sec_periphs_sec_status &= ~slave_vector;
else
tz_sec_periphs_sec_status |= slave_vector;
val = tz_sec_periphs_sec_status & mask;
write32((void *)AXIIC_APBZ_s0_security, val);
}
/*
* Set external slave security.
* Use defines in tz.h for both parameters.
*/
void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
{
uint32_t val;
uint32_t mask_s0 = AXIIC_ext_s0_security_MASK;
uint32_t mask_s1 = AXIIC_ext_s1_security_MASK;
uint32_t tz_ext_slaves_sec_status =
(mask_s0 & read32((void *)AXIIC_ext_s0_security)) |
((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_ext_slaves_sec_status &= ~slave_vector;
else
tz_ext_slaves_sec_status |= slave_vector;
val = tz_ext_slaves_sec_status & mask_s0;
write32((void *)AXIIC_ext_s0_security, val);
val = (tz_ext_slaves_sec_status >> 16) & mask_s1;
write32((void *)AXIIC_ext_s1_security, val);
}
/*
* Set cfg slave security
* Use defines in tz.h for both parameters.
*/
void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
{
uint32_t val;
uint32_t mask_r = AXIIC_APBR_s0_security_MASK;
uint32_t mask_s = AXIIC_APBS_s0_security_MASK;
uint32_t tz_cfg_slaves_sec_status =
(mask_r & read32((void *)AXIIC_APBR_s0_security)) |
((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_cfg_slaves_sec_status &= ~slave_vector;
else
tz_cfg_slaves_sec_status |= slave_vector;
val = tz_cfg_slaves_sec_status & mask_r;
write32((void *)AXIIC_APBR_s0_security, val);
val = (tz_cfg_slaves_sec_status >> 16) & mask_s;
write32((void *)AXIIC_APBS_s0_security, val);
}
/*
* Set SRAM secure region
* parameter 'r0size' specify the secure RAM region in 4KB steps:
* 0x00000000 = no secure region
* 0x00000001 = 4KB secure region
* 0x00000002 = 8KB secure region
* .......
* 0x000001FF = 2044KB secure region.
* 0x00000200 or above sets the entire SRAM to secure regardless of size
*/
void tz_set_sram_sec_region(uint32_t r0size)
{
uint32_t mask = TZPC_TZPCR0SIZE_MASK;
write32((void *)TZPC_TZPCR0SIZE, r0size & mask);
}
/*
* Set wrapper security
* Use defines in tz.h for all parameters.
*/
void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2,
uint32_t wrapper3, uint32_t wrapper4,
uint32_t ns_bit)
{
uint32_t mask_w4 = AXIIC_APB_W4_security_MASK;
uint32_t mask_w3 = AXIIC_APB_W3_security_MASK;
uint32_t mask_w2 = AXIIC_APB_W2_security_MASK;
uint32_t mask_w1 = AXIIC_APB_W1_security_MASK;
uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security);
uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security);
uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security);
uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security);
if (ns_bit == TZ_STATE_SECURE) {
tz_wrapper1_sec_status &= ~wrapper1;
tz_wrapper2_sec_status &= ~wrapper2;
tz_wrapper3_sec_status &= ~wrapper3;
tz_wrapper4_sec_status &= ~wrapper4;
} else {
tz_wrapper1_sec_status |= wrapper1;
tz_wrapper2_sec_status |= wrapper2;
tz_wrapper3_sec_status |= wrapper3;
tz_wrapper4_sec_status |= wrapper4;
}
write32((void *)AXIIC_APB_W1_security,
tz_wrapper1_sec_status & mask_w1);
write32((void *)AXIIC_APB_W2_security,
tz_wrapper2_sec_status & mask_w2);
write32((void *)AXIIC_APB_W3_security,
tz_wrapper3_sec_status & mask_w3);
write32((void *)AXIIC_APB_W4_security,
tz_wrapper4_sec_status & mask_w4);
}

166
src/soc/broadcom/cygnus/usb.c
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@ -1,166 +0,0 @@
/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <console/console.h>
#include <soc/cygnus.h>
#define CDRU_USBPHY_CLK_RST_SEL_OFFSET 0x11b4
#define CDRU_USBPHY2_HOST_DEV_SEL_OFFSET 0x11b8
#define CDRU_SPARE_REG_0_OFFSET 0x1238
#define CRMU_USB_PHY_AON_CTRL_OFFSET 0x00028
#define CDRU_USB_DEV_SUSPEND_RESUME_CTRL_OFFSET 0x1210
#define CDRU_USBPHY_P2_STATUS_OFFSET 0x1200
#define CDRU_USB_DEV_SUSPEND_RESUME_CTRL_DISABLE 0
#define PHY2_DEV_HOST_CTRL_SEL_DEVICE 0
#define PHY2_DEV_HOST_CTRL_SEL_HOST 1
#define CDRU_USBPHY_P2_STATUS__USBPHY_ILDO_ON_FLAG 1
#define CDRU_USBPHY_P2_STATUS__USBPHY_PLL_LOCK 0
#define CRMU_USBPHY_P0_AFE_CORERDY_VDDC 1
#define CRMU_USBPHY_P0_RESETB 2
#define CRMU_USBPHY_P1_AFE_CORERDY_VDDC 9
#define CRMU_USBPHY_P1_RESETB 10
#define CRMU_USBPHY_P2_AFE_CORERDY_VDDC 17
#define CRMU_USBPHY_P2_RESETB 18
#define USB2_IDM_IDM_IO_CONTROL_DIRECT_OFFSET 0x0408
#define USB2_IDM_IDM_IO_CONTROL_DIRECT__clk_enable 0
#define USB2_IDM_IDM_RESET_CONTROL_OFFSET 0x0800
#define USB2_IDM_IDM_RESET_CONTROL__RESET 0
#define PLL_LOCK_RETRY_COUNT 1000
#define MAX_REGULATOR_NAME_LEN 25
#define NUM_PHYS 3
struct bcm_phy_instance {
struct phy *generic_phy;
int port;
int host_mode; /* 1 - Host, 0 - device */
int power; /* 1 -powered_on 0 -powered off */
struct regulator *vbus_supply;
};
struct bcm_phy_driver {
void *usbphy_regs;
void *usb2h_idm_regs;
void *usb2d_idm_regs;
int num_phys, idm_host_enabled;
struct bcm_phy_instance instances[NUM_PHYS];
};
static struct bcm_phy_driver phy_driver;
static int bcm_phy_init(struct bcm_phy_instance *instance_ptr)
{
/* Only PORT 2 is capabale of being device and host
* Default setting is device, check if it is set to host */
if (instance_ptr->port == 2) {
if (instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_HOST)
write32(phy_driver.usbphy_regs + CDRU_USBPHY2_HOST_DEV_SEL_OFFSET,
PHY2_DEV_HOST_CTRL_SEL_HOST);
else
die("usb device mode unsupported\n");
}
return 0;
}
static int bcm_phy_poweron(struct bcm_phy_instance *instance_ptr)
{
int clock_reset_flag = 1;
u32 val;
/* Bring the AFE block out of reset to start powering up the PHY */
val = read32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET);
if (instance_ptr->port == 0)
val |= (1 << CRMU_USBPHY_P0_AFE_CORERDY_VDDC);
else if (instance_ptr->port == 1)
val |= (1 << CRMU_USBPHY_P1_AFE_CORERDY_VDDC);
else if (instance_ptr->port == 2)
val |= (1 << CRMU_USBPHY_P2_AFE_CORERDY_VDDC);
write32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET, val);
instance_ptr->power = 1;
/* Check if the port 2 is configured for device */
if (instance_ptr->port == 2 &&
instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_DEVICE)
die("usb device mode unsupported\n");
val = read32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET);
/* Check if the phy that is configured
* to provide clock and reset is powered on*/
if (val >= 0 && val < phy_driver.num_phys) {
if (phy_driver.instances[val].power == 1)
clock_reset_flag = 0;
}
/* if not set the current phy */
if (clock_reset_flag) {
val = instance_ptr->port;
write32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET,
val);
}
if (phy_driver.idm_host_enabled != 1) {
/* Enable clock to USB and get the USB out of reset */
setbits_le32(phy_driver.usb2h_idm_regs +
USB2_IDM_IDM_IO_CONTROL_DIRECT_OFFSET,
(1 << USB2_IDM_IDM_IO_CONTROL_DIRECT__clk_enable));
clrbits_le32(phy_driver.usb2h_idm_regs +
USB2_IDM_IDM_RESET_CONTROL_OFFSET,
(1 << USB2_IDM_IDM_RESET_CONTROL__RESET));
phy_driver.idm_host_enabled = 1;
}
return 0;
}
static int bcm_phy_probe(void)
{
int i;
phy_driver.num_phys = NUM_PHYS;
phy_driver.usbphy_regs = (void *)0x0301c000;
phy_driver.usb2h_idm_regs = (void *)0x18115000;
phy_driver.usb2d_idm_regs = (void *)0x18111000;
phy_driver.idm_host_enabled = 0;
/* Shutdown all ports. They can be powered up as required */
clrbits_le32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET,
(1 << CRMU_USBPHY_P0_AFE_CORERDY_VDDC) |
(1 << CRMU_USBPHY_P0_RESETB) |
(1 << CRMU_USBPHY_P1_AFE_CORERDY_VDDC) |
(1 << CRMU_USBPHY_P1_RESETB) |
(1 << CRMU_USBPHY_P2_AFE_CORERDY_VDDC) |
(1 << CRMU_USBPHY_P2_RESETB));
for (i = 0; i < phy_driver.num_phys; i++) {
phy_driver.instances[i].port = i;
phy_driver.instances[i].host_mode = PHY2_DEV_HOST_CTRL_SEL_HOST;
}
return 0;
}
void usb_init(void)
{
bcm_phy_probe();
/* currently, we only need thus support port 0 */
bcm_phy_init(&phy_driver.instances[0]);
bcm_phy_poweron(&phy_driver.instances[0]);
printk(BIOS_INFO, "usb phy[%d] is powered on\n", 0);
}

170
src/soc/broadcom/cygnus/ydc_ddr_bist.c
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@ -1,170 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/cygnus_types.h>
#include <console/console.h>
#define SOC_IF_ERROR_RETURN(x) (x)
#define sal_alloc(x,y) malloc(x)
#define sal_memset(x,y,z) memset(x,y,z)
#define sal_free(x) free(x)
#define sal_usleep(x) udelay(x)
/* BEGIN: TEMPORARY */
#ifndef BCM_AND28_SUPPORT
#define BCM_AND28_SUPPORT
#endif
/* END: TEMPORARY */
#ifdef BCM_AND28_SUPPORT
#include <soc/shmoo_and28/ydc_ddr_bist.h>
#include <soc/shmoo_and28/phy_reg_access.h>
#endif
/* BEGIN: HELPER FUNCTIONS */
static uint32
_get_random28(void)
{
static uint32 m_w = 6483; /* must not be zero */
static uint32 m_z = 31245; /* must not be zero */
m_z = 36969 * (m_z & 65535) + (m_z >> 16);
m_w = 18000 * (m_w & 65535) + (m_w >> 16);
return (m_z << 16) + m_w; /* 32-bit result */
}
/* END: HELPER FUNCTIONS */
int
soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_info)
{
uint32 data;
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, WRITE_WEIGHT, (*bist_info).write_weight);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, READ_WEIGHT, (*bist_info).read_weight);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PATTERN_BIT_MODE, 0);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PRBS_MODE, (*bist_info).prbs_mode);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, CONS_ADDR_8_BANKS, 1);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, ADDRESS_SHIFT_MODE, 0);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_SHIFT_MODE, 0);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_ADDR_MODE, 0);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, IND_WR_RD_ADDR_MODE, 1);
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
if (!((*bist_info).prbs_mode))
{
if ((*bist_info).mpr_mode)
{
if (YDC_DDR_BIST_PHY_BITWITDH_IS_32)
{
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
}
else
{
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
}
}
else
{
WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
}
}
READ_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, NUMBER_OF_ACTIONS, BIST_NUM_ACTIONS, (*bist_info).bist_num_actions);
WRITE_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, data);
READ_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, START_ADDRESS, BIST_START_ADDRESS, (*bist_info).bist_start_address);
WRITE_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
READ_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, END_ADDRESS, BIST_END_ADDRESS, (*bist_info).bist_end_address);
WRITE_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
return SOC_E_NONE;
}
int
soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count)
{
uint32 data;
uint32 poll_count;
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 1);
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
poll_count = 0;
while (TRUE)
{
READ_YDC_DDR_BIST_STATUSESr(0, YDC_DDR_BIST_REG_BASE, &data);
if (YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, STATUSES, BIST_FINISHED))
{
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
break;
}
if (poll_count > YDC_DDR_BIST_POLL_COUNT_LIMIT)
{
READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
printk(BIOS_ERR, "ERROR: YDC DDR BIST timeout!!!\n");
return SOC_E_TIMEOUT;
}
poll_count++;
sal_usleep(YDC_DDR_BIST_POLL_INTERVAL_US);
}
READ_YDC_DDR_BIST_ERROR_OCCURREDr(0, YDC_DDR_BIST_REG_BASE, &data);
(*error_count).bist_err_occur = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, ERROR_OCCURRED, ERR_OCCURRED);
READ_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
(*error_count).bist_full_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, FULL_MASK_ERROR_COUNTER, FULL_ERR_CNT);
READ_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
(*error_count).bist_single_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, SINGLE_BIT_MASK_ERROR_COUNTER, SINGLE_ERR_CNT);
READ_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
(*error_count).bist_global_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, GLOBAL_ERROR_COUNTER, GLOBAL_ERR_CNT);
return SOC_E_NONE;
}

1
util/README.md
View File

@ -16,7 +16,6 @@ Technologies, for example the Pistachio SoC. `C`
`Yacc`
* __board_status__ - Tools to collect logs and upload them to the board
status repository `Bash` `Go`
* __broadcom__ - Generate Broadcom secure boot image. `C`
* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
file `Python`
* __cbfstool__

1
util/broadcom/Makefile.inc
View File

@ -1 +0,0 @@
subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += secimage

1
util/broadcom/description.md
View File

@ -1 +0,0 @@
Generate Broadcom secure boot image. `C`

BIN
util/broadcom/khmacsha256
View File

Binary file not shown.

42
util/broadcom/secimage/Makefile
View File

@ -1,42 +0,0 @@
#
# Copyright (C) 2015 Broadcom Corporation
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation version 2.
#
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
# kind, whether express or implied; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
TARGET = secimage
OBJS = crypto.o io.o misc.o sbi.o
CC = gcc
RM = rm
CFLAGS += -Wall -g
LIBS = -lssl -lcrypto -lz
%.o : %.c
$(CC) -c $(CFLAGS) -o $@ $<
all: $(TARGET)
$(TARGET): $(OBJS)
$(CC) -o $@ $(OBJS) $(LIBS)
install:
install -d $(DESTDIR)/usr/bin
install $(TARGET) $(DESTDIR)/usr/bin
.PHONY: test
test: $(TARGET)
@find test -maxdepth 1 -type f -executable \
| xargs -I "{}" sh -c "{} $$(realpath $<)"
.PHONY: clean distclean
clean distclean:
$(RM) -f $(TARGET) $(OBJS)

18
util/broadcom/secimage/Makefile.inc
View File

@ -1,18 +0,0 @@
secimageobj :=
secimageobj += crypto.o
secimageobj += io.o
secimageobj += misc.o
secimageobj += sbi.o
LIBS = -lssl -lcrypto -lz
additional-dirs += $(objutil)/broadcom/secimage
$(objutil)/broadcom/secimage/%.o: $(top)/util/broadcom/secimage/%.c
printf " HOSTCC $(subst $(objutil)/,,$(@))\n"
$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
$(objutil)/broadcom/secimage/secimage: \
$(addprefix $(objutil)/broadcom/secimage/,$(secimageobj))
printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n"
$(HOSTCC) -o $@ $^ $(LIBS)

68
util/broadcom/secimage/crypto.c
View File

@ -1,68 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "secimage.h"
#include <openssl/hmac.h>
/*----------------------------------------------------------------------
* Name : HmacSha256Hash
* Purpose :
* Input : none
* Output : none
*---------------------------------------------------------------------*/
int HmacSha256Hash(uint8_t *data, uint32_t len, uint8_t *hash, uint8_t *key)
{
unsigned int hash_len = 0;
if (!HMAC(EVP_sha256(), key, 32, data, len, hash, &hash_len)) {
printf("HMAC failed\n");
return -1;
} else if (hash_len != 32) {
printf("HMAC reported unexpected md_len of %u\n", hash_len);
return -2;
}
return 0;
}
/*----------------------------------------------------------------------
* Name : AppendHMACSignature
* Purpose : Appends HMAC signature at the end of the data
*---------------------------------------------------------------------*/
int AppendHMACSignature(uint8_t *data, uint32_t length, char *filename,
uint32_t offset)
{
uint8_t hmackey[32];
uint32_t len;
uint32_t status;
uint8_t *digest = data + length;
len = ReadBinaryFile(filename, hmackey, 32);
if (len != 32) {
printf("Error reading hmac key file\n");
return 0;
}
status = HmacSha256Hash(&data[offset], length - offset, digest,
hmackey);
if (status) {
printf("HMAC-SHA256 hash error\n");
return 0;
}
return 32;
}

123
util/broadcom/secimage/io.c
View File

@ -1,123 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include "secimage.h"
/*----------------------------------------------------------------------
* Name : ReadBinaryFile
* Purpose : Read some data from file of raw binary
* Input : fname : file to be read
* buf : buffer which is the data desitnation
* maxlen : maiximum length of data to be read
* Output : none
*---------------------------------------------------------------------*/
int ReadBinaryFile(char *fname, uint8_t *buf, int maxlen)
{
FILE *fp = NULL;
int len = 0;
fp = fopen(fname, "rb");
if (fp == NULL)
return 0;
printf("fname=%s, len=%d\n", fname, maxlen);
len = fread(buf, 1, maxlen, fp);
fclose(fp);
return len;
}
/*----------------------------------------------------------------------
* Name : FileSizeGet
* Purpose : Return the size of the file
* Input : file: FILE * to the file to be processed
* Output : none
*---------------------------------------------------------------------*/
size_t FileSizeGet(FILE *file)
{
long length;
fseek(file, 0, SEEK_END);
length = ftell(file);
rewind(file);
return (size_t)length;
}
/*----------------------------------------------------------------------
* Name : DataRead
* Purpose : Read all the data from a file
* Input : filename : file to be read
* buf : buffer which is the data destination
* length : length of data to be read
* Output : none
*---------------------------------------------------------------------*/
int DataRead(char *filename, uint8_t *buf, int *length)
{
FILE *file;
int len = *length;
file = fopen(filename, "rb");
if (file == NULL) {
printf("Unable to open file: %s\n", filename);
return -1;
}
len = FileSizeGet(file);
if (len < 0) {
printf("Unable to seek in file: %s\n", filename);
fclose(file);
return -1;
}
if (len < *length)
*length = len;
else
/* Do not exceed the maximum length of the buffer */
len = *length;
if (fread((uint8_t *)buf, 1, len, file) != len) {
printf("Error reading data (%d bytes) from file: %s\n",
len, filename);
fclose(file);
return -1;
}
fclose(file);
return 0;
}
/*----------------------------------------------------------------------
* Name : DataWrite
* Purpose : Write some binary data to a file
* Input : filename : file to be written
* buf : buffer which is the data source
* length : length of data to be written
* Output : none
*---------------------------------------------------------------------*/
int DataWrite(char *filename, char *buf, int length)
{
FILE *file;
file = fopen(filename, "wb");
if (file == NULL) {
printf("Unable to open output file %s\n", filename);
return -1;
}
if (fwrite(buf, 1, length, file) < length) {
printf("Unable to write %d bytes to output file %s (0x%X).\n",
length, filename, ferror(file));
fclose(file);
return -1;
}
fflush(file);
fclose(file);
return 0;
}

58
util/broadcom/secimage/misc.c
View File

@ -1,58 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include "secimage.h"
static unsigned char filebuffer[2049];
void FillHeaderFromConfigFile(char *h, char *ConfigFileName)
{
int byte_count = 0;
char *ptr;
FILE *fp;
unsigned int Tag;
unsigned int Length;
unsigned int Reserved;
HEADER *h1 = (HEADER *)h;
fp = fopen(ConfigFileName, "rb");
if (fp != NULL) {
printf("\r\n Reading config information from file \r\n");
byte_count = fread(filebuffer, 1, 2048, fp);
filebuffer[2048] = 0;
if (byte_count > 0) {
ptr = strstr((char *)filebuffer, "Tag=");
if (ptr) {
ptr += strlen("Tag=");
sscanf(ptr, "%x", &Tag);
h1->Tag = Tag;
}
ptr = strstr((char *)filebuffer, "Length=");
if (ptr) {
ptr += strlen("Length=");
sscanf(ptr, "%x", &Length);
h1->Length = Length;
}
ptr = strstr((char *)filebuffer, "Reserved=");
if (ptr) {
ptr += strlen("Reserved=");
sscanf(ptr, "%x", &Reserved);
h1->Reserved = Reserved;
}
}
fclose(fp);
}
}

197
util/broadcom/secimage/sbi.c
View File

@ -1,197 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <zlib.h>
#include "secimage.h"
#define MIN_SIZE (1024*120)
/*----------------------------------------------------------------------
* Name : SBIUsage
* Purpose :
* Input : none
* Output : none
*---------------------------------------------------------------------*/
int SBIUsage(void)
{
printf("\nTo create a Secure Boot Image:\n");
printf("secimage: -out <output binary> [-hmac hmac_binary_key] <-config configfile>");
printf("\n\t\t[-bl input binary]\n");
return 0;
}
/*----------------------------------------------------------------------
* Name : AddImagePayload
* Purpose :
* Input : none
* Output : none
*---------------------------------------------------------------------*/
int AddImagePayload(char *h, char *filename, unsigned int filesize)
{
uint32_t totalLen;
int length = filesize;
int padlen = 0;
int status = 0;
totalLen = 0x40;
status = DataRead(filename, (uint8_t *)h + totalLen, &length);
printf("\r\n Adding file %s ... \r\n", filename);
if (!status) {
if (length & 15) {
padlen = 16 - (length & 15);
memset((uint8_t *)h + totalLen + length, 0, padlen);
length += padlen;
}
*(uint32_t *)&h[FIELD5_OFFSET] = length;
*(uint32_t *)&h[FIELD6_OFFSET] += length;
} else
printf("Error reading image Payload from %s\n", filename);
return status;
}
/*----------------------------------------------------------------------
* Name : CreateSecureBootImage
* Purpose :
* Input : none
* Output : none
*---------------------------------------------------------------------*/
int CreateSecureBootImage(int ac, char **av)
{
char *configfile = NULL, *arg, *privkey = NULL, *bl = NULL;
int status = 0;
uint32_t sbiLen;
struct stat file_stat;
uint32_t add_header = 1;
char *outfile = *av;
unsigned int filesize;
char *buf;
--ac; ++av;
if (ac <= 0)
return SBIUsage();
while (ac) {
arg = *av;
if (!strcmp(arg, "-bl")) {
--ac, ++av;
bl = *av;
} else if (!strcmp(arg, "-hmac")) {
--ac, ++av;
privkey = *av;
} else if (!strcmp(arg, "-config")) {
--ac, ++av;
configfile = *av;
} else if (!strcmp(arg, "-noheader")) {
add_header = 0;
} else {
return SBIUsage();
}
--ac, ++av;
}
if (!bl) {
puts("-bl not set");
return -1;
}
if (!privkey) {
puts("-hmac not set");
return -1;
}
if (stat(bl, &file_stat) == -1) {
puts("Can't stat bl");
return -1;
}
filesize = file_stat.st_size + MIN_SIZE;
buf = calloc(sizeof(uint8_t), filesize);
if (buf == NULL) {
puts("Memory allocation error");
status = -1;
goto done;
}
*(uint32_t *)&buf[FIELD6_OFFSET] = 0x40;
*(uint32_t *)&buf[FIELD9_OFFSET] = 0x45F2D99A;
*(uint32_t *)&buf[FIELD3_OFFSET] = 0x900FFFFF;
*(uint16_t *)&buf[FIELD1_OFFSET] = 0x40;
*(uint32_t *)&buf[FIELD4_OFFSET] = 0x40;
*(uint16_t *)&buf[FIELD2_OFFSET] = 0x10;
*(uint16_t *)&buf[FIELD8_OFFSET] = 0x20;
*(uint16_t *)&buf[FIELD7_OFFSET] = 0x10;
if (status == 0) {
if (configfile)
FillHeaderFromConfigFile(buf, configfile);
status = AddImagePayload(buf, bl, filesize);
if (status) {
status = -1;
goto done;
}
sbiLen = *(uint32_t *)&buf[FIELD6_OFFSET];
printf("HMAC signing %d bytes\n", sbiLen);
status = AppendHMACSignature((uint8_t *)buf, sbiLen, privkey,
add_header ? 0x10 : 0x40);
if (status > 0) {
sbiLen += status;
status = 0;
}
if (!status) {
((HEADER *)buf)->Length = sbiLen;
((HEADER *)buf)->crc = crc32(0xFFFFFFFF,
(uint8_t *)buf, 12);
printf("Generating Image file %s: %d bytes\n",
outfile, sbiLen);
if (!add_header)
status = DataWrite(outfile, &buf[0x40],
sbiLen - 0x40);
else
status = DataWrite(outfile, buf, sbiLen);
}
}
if (status < 0)
printf("Generation error %d\n", status);
done:
free(buf);
return status;
}
int main(int argc, char **argv)
{
argc--;
argv++;
if (argc > 0) {
if (!strcmp(*argv, "-out"))
return CreateSecureBootImage(--argc, ++argv);
}
SBIUsage();
return 0;
}

44
util/broadcom/secimage/secimage.h
View File

@ -1,44 +0,0 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SECIMAGE_H_
#define _SECIMAGE_H_
#include <stdint.h>
#include <sys/types.h>
#define FIELD1_OFFSET 16
#define FIELD2_OFFSET 18
#define FIELD3_OFFSET 20
#define FIELD4_OFFSET 36
#define FIELD5_OFFSET 40
#define FIELD6_OFFSET 44
#define FIELD7_OFFSET 48
#define FIELD8_OFFSET 50
#define FIELD9_OFFSET 60
typedef struct Header_t {
uint32_t Tag;
uint32_t Length;
uint32_t Reserved;
uint32_t crc;
} HEADER;
int DataWrite(char *filename, char *buf, int length);
int DataRead(char *filename, uint8_t *buf, int *length);
int AppendHMACSignature(uint8_t *data, uint32_t length, char *filename,
uint32_t offset);
int ReadBinaryFile(char *fname, uint8_t *buf, int maxlen);
void FillHeaderFromConfigFile(char *h, char *ConfigFileName);
#endif /* _SECIMAGE_H_ */

1097
util/broadcom/secimage/test/data/expected/binary.xxdump
View File

File diff suppressed because it is too large Load Diff

1091
util/broadcom/secimage/test/data/input/binary.xxdump
View File

File diff suppressed because it is too large Load Diff

41
util/broadcom/secimage/test/data/input/configfile.xxdump
View File

@ -1,41 +0,0 @@
00000000: 2f2f 2055 6e61 7574 6820 4865 6164 6572 // Unauth Header |
00000010: 0a2f 2f0a 2f2f 2073 7472 7563 7420 556e .//.// struct Un |
00000020: 4175 7468 656e 7469 6361 7465 6448 6561 AuthenticatedHea |
00000030: 6465 725f 7420 7b0a 2f2f 0975 696e 7433 der_t {.//.uint3 |
00000040: 325f 7420 5461 673b 0909 2f2a 2054 6167 2_t Tag;../* Tag |
00000050: 2075 7365 6420 746f 206c 6f63 6174 6520 used to locate |
00000060: 626f 6f74 2062 696e 6172 7920 696e 206d boot binary in m |
00000070: 656d 6f72 7920 2a2f 0a2f 2f09 7569 6e74 emory */.//.uint |
00000080: 3332 5f74 204c 656e 6774 683b 092f 2a20 32_t Length;./* |
00000090: 4c65 6e67 7468 206f 6620 7468 6520 626f Length of the bo |
000000a0: 6f74 2062 696e 6172 7920 2a2f 0a2f 2f09 ot binary */.//. |
000000b0: 7569 6e74 3332 5f74 2052 6573 6572 7665 uint32_t Reserve |
000000c0: 643b 092f 2a20 4164 6472 6573 7320 666f d;./* Address fo |
000000d0: 7220 7468 6520 6e6f 6e2d 6175 7468 656e r the non-authen |
000000e0: 7469 6361 7465 6420 626f 6f74 2e0a 2f2f ticated boot..// |
000000f0: 0909 0909 2020 2054 6865 2061 6464 7265 .... The addre |
00000100: 7373 2069 7320 616c 6967 6e65 6420 746f ss is aligned to |
00000110: 2031 3620 6279 7465 7320 626f 756e 6461 16 bytes bounda |
00000120: 7279 2e0a 2f2f 0909 0909 2020 2054 6865 ry..//.... The |
00000130: 206c 6f77 6572 2034 2062 6974 7320 6172 lower 4 bits ar |
00000140: 6520 7573 6564 2066 6f72 2043 6c6b 436f e used for ClkCo |
00000150: 6e66 6967 3a0a 2f2f 0909 0909 2020 2056 nfig:.//.... V |
00000160: 616c 7565 2020 2046 7265 710a 2f2f 0909 alue Freq.//.. |
00000170: 0909 2020 2031 2020 2020 2020 2034 3030 .. 1 400 |
00000180: 0a2f 2f09 0909 0920 2020 3220 2020 2020 .//.... 2 |
00000190: 2020 3147 487a 0a2f 2f09 0909 0920 2020 1GHz.//.... |
000001a0: 3320 2020 2020 2020 4d61 7820 2831 2e32 3 Max (1.2 |
000001b0: 4748 7a29 0a2f 2f09 0909 0920 2020 3420 GHz).//.... 4 |
000001c0: 2020 2020 2020 6e6f 2050 4c4c 206c 6f63 no PLL loc |
000001d0: 6b3a 2032 3030 4d48 7a0a 2f2f 0909 0909 k: 200MHz.//.... |
000001e0: 202a 2f0a 2f2f 0975 696e 7433 325f 7420 */.//.uint32_t |
000001f0: 6372 633b 0909 2f2a 2043 5243 2063 6f6d crc;../* CRC com |
00000200: 7075 7465 6420 6f6e 2061 6c6c 206f 7468 puted on all oth |
00000210: 6572 2066 6965 6c64 7320 696e 2074 6869 er fields in thi |
00000220: 730a 2f2f 0909 0909 2020 2073 7472 7563 s.//.... struc |
00000230: 7475 7265 2065 7863 6c75 6469 6e67 2063 ture excluding c |
00000240: 7263 2066 6965 6c64 202a 2f0a 2f2f 207d rc field */.// } |
00000250: 3b0a 5461 673d 0909 3078 4135 4135 4135 ;.Tag=..0xA5A5A5 |
00000260: 4135 0a4c 656e 6774 683d 0909 3078 3030 A5.Length=..0x00 |
00000270: 3030 3030 3030 0a52 6573 6572 7665 643d 000000.Reserved= |
00000280: 2020 0930 7830 3030 3030 3030 320a .0x00000002. |

2
util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump
View File

@ -1,2 +0,0 @@
00000000: d1ef bcba d798 d871 003d ee3b f7b8 461c .......q.=.;..F. |
00000010: 53a8 b9c5 b6dc 57dc 1280 631d aea3 e003 S.....W...c..... |

78
util/broadcom/secimage/test/hmac.sh
View File

@ -1,78 +0,0 @@
#!/usr/bin/env bash
##
## This file is part of the coreboot project.
##
## Copyright (C) 2003-2018 Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 3 or later of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-3.0-or-later
## <https://spdx.org/licenses/GPL-3.0-or-later.html>
##
set -o errexit
set -o nounset
set -o pipefail
# static analysis
if command -v shellcheck 1>/dev/null; then
shellcheck "${BASH_SOURCE[0]}"
else
echo "shellcheck not found, running unchecked" >&2
fi
# dependency check
dependencies=(basename diff dirname head mkdir mktemp openssl rm tail xxd)
for dependency in "${dependencies[@]}"; do
if ! command -v "${dependency}" 1>/dev/null; then
echo "missing ${dependency}, test skipped" >&2
exit 0
fi
done
# parameters
if [ ${#} -ne 1 ]; then
echo "usage: '${0}' <testee>"
exit 1
fi
# setup
testee="${1}"
declare -i header_len=16 signature_len=32
tmp_dir="$(mktemp --directory --tmpdir secimage-test-XXXXXXXX)"
shopt -s globstar nullglob
for dump_file in test/data/**/*.xxdump; do
bin_file_dir="${tmp_dir}/$(dirname "${dump_file#test/data/}")"
mkdir --parents "${bin_file_dir}"
xxd -r "${dump_file}" \
"${bin_file_dir}/$(basename "${dump_file}" .xxdump)"
done
tail --bytes=+$((header_len + 1)) "${tmp_dir}/expected/binary" \
| head --bytes=-${signature_len} \
| openssl dgst -sha256 -mac hmac \
-macopt hexkey:"$(xxd -c$((signature_len * 2)) -ps \
"${tmp_dir}/input/hmac_binary_key")" \
-binary \
> "${tmp_dir}/expected/signature"
mkdir "${tmp_dir}/actual"
# test
"${testee}" \
-out "${tmp_dir}/actual/binary" \
-config "${tmp_dir}/input/configfile" \
-hmac "${tmp_dir}/input/hmac_binary_key" \
-bl "${tmp_dir}/input/binary"
tail --bytes=${signature_len} "${tmp_dir}/actual/binary" \
> "${tmp_dir}/actual/signature"
diff --recursive "${tmp_dir}/actual" "${tmp_dir}/expected" 1>/dev/null
# teardown
rm --force --recursive "${tmp_dir}"

20
util/broadcom/unauth.cfg
View File

@ -1,20 +0,0 @@
// Unauth Header
//
// struct UnAuthenticatedHeader_t {
// uint32_t Tag; /* Tag used to locate boot binary in memory */
// uint32_t Length; /* Length of the boot binary */
// uint32_t Reserved; /* Address for the non-authenticated boot.
// The address is aligned to 16 bytes boundary.
// The lower 4 bits are used for ClkConfig:
// Value Freq
// 1 400
// 2 1GHz
// 3 Max (1.2GHz)
// 4 no PLL lock: 200MHz
// */
// uint32_t crc; /* CRC computed on all other fields in this
// structure excluding crc field */
// };
Tag= 0xA5A5A5A5
Length= 0x00000000
Reserved= 0x00000002

1
util/testing/Makefile.inc
View File

@ -60,7 +60,6 @@ junit.xml:
echo
TOOLLIST= \
broadcom/secimage \
cbmem \
ectool \
futility \