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soc/amd/picasso: remove warm reset flag code 

Since the MCA(X) registers have defined values on the cold boot path,
the is_warm_reset check can be dropped. Also the warm reset bit in the
NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if
something was written to the register or the machine went through a warm
reset cycle, the NCP_WARM_BOOT bit never got set.

[1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO)
#55570 Rev 3.15

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-05-28 19:10:13 +02:00
parent 71971c9d7e
commit aea59401d0
5 changed files with 25 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/picasso/cpu.c
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@ -59,8 +59,6 @@ void mp_init_cpus(struct bus *cpu_bus)
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
set_warm_reset_flag();
} }
static void model_17_init(struct device *dev) static void model_17_init(struct device *dev)

1
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -83,7 +83,6 @@
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
#define NCP_ERR 0xf0
#define SMB_BASE_ADDR 0xb00 #define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0 #define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1 #define PM2_DATA 0xcd1

3
src/soc/amd/picasso/include/soc/southbridge.h
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@ -140,9 +140,6 @@
#define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12) #define SATA_CAPABILITY_SPM BIT(12)
/* IO 0xf0 NCP Error */
#define NCP_WARM_BOOT BIT(7) /* Write-once */
typedef struct aoac_devs { typedef struct aoac_devs {
unsigned int :7; unsigned int :7;
unsigned int ic2e:1; /* 7: I2C2 */ unsigned int ic2e:1; /* 7: I2C2 */

52
src/soc/amd/picasso/mca.c
View File

@ -159,36 +159,34 @@ void check_mca(void)
cap = rdmsr(IA32_MCG_CAP); cap = rdmsr(IA32_MCG_CAP);
num_banks = cap.lo & MCA_BANKS_MASK; num_banks = cap.lo & MCA_BANKS_MASK;
if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) {
for (i = 0 ; i < num_banks ; i++) { mci.sts = rdmsr(MCAX_STATUS_MSR(i));
mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) {
if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24;
int core = cpuid_ebx(1) >> 24;
printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",
core, i, core, i,
i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : "");
printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",
i, mci.sts.hi, mci.sts.lo); i, mci.sts.hi, mci.sts.lo);
mci.addr = rdmsr(MCAX_ADDR_MSR(i)); mci.addr = rdmsr(MCAX_ADDR_MSR(i));
printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",
i, mci.addr.hi, mci.addr.lo); i, mci.addr.hi, mci.addr.lo);
mci.misc = rdmsr(MCAX_MISC0_MSR(i)); mci.misc = rdmsr(MCAX_MISC0_MSR(i));
printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",
i, mci.misc.hi, mci.misc.lo); i, mci.misc.hi, mci.misc.lo);
mci.ctl = rdmsr(MCAX_CTL_MSR(i)); mci.ctl = rdmsr(MCAX_CTL_MSR(i));
printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n",
i, mci.ctl.hi, mci.ctl.lo); i, mci.ctl.hi, mci.ctl.lo);
mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i));
printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",
i, mci.cmask.hi, mci.cmask.lo); i, mci.cmask.hi, mci.cmask.lo);
mci.bank = i; mci.bank = i;
if (CONFIG(ACPI_BERT) if (CONFIG(ACPI_BERT)
&& mca_valid(mci.sts)) && mca_valid(mci.sts))
build_bert_mca_error(&mci); build_bert_mca_error(&mci);
}
} }
} }

14
src/soc/amd/picasso/reset.c
View File

@ -7,18 +7,6 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h> #include <amdblocks/reset.h>
void set_warm_reset_flag(void)
{
uint8_t ncp = inb(NCP_ERR);
outb(NCP_ERR, ncp | NCP_WARM_BOOT);
}
int is_warm_reset(void)
{
return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
}
void do_cold_reset(void) void do_cold_reset(void)
{ {
/* De-assert and then assert all PwrGood signals on CF9 reset. */ /* De-assert and then assert all PwrGood signals on CF9 reset. */
@ -29,8 +17,6 @@ void do_cold_reset(void)
void do_warm_reset(void) void do_warm_reset(void)
{ {
set_warm_reset_flag();
/* Assert reset signals only. */ /* Assert reset signals only. */
outb(RST_CPU | SYS_RST, RST_CNT); outb(RST_CPU | SYS_RST, RST_CNT);
} }