nb/intel/i440bx: Switch to POSTCAR_STAGE
Boot tested on asus/p2b-ls and p2b-ds. Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26821 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kyösti Mälkki
parent
546990710c
commit
aea8eecded
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@ -23,6 +23,9 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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@ -165,118 +168,11 @@ before_romstage:
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post_code(0x2f)
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/* Call romstage.c main function. */
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call romstage_main
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/* Save return value from romstage_main. It contains the stack to use
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* after cache-as-ram is torn down. It also contains the information
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* for setting up MTRRs. */
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movl %eax, %esp
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post_code(0x30)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~MTRR_DEF_TYPE_EN), %eax
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wrmsr
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post_code(0x32)
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invd
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post_code(0x33)
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/* Enable cache. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Clear all of the variable MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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clr %eax
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clr %edx
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1:
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testl %ebx, %ebx
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jz 1f
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wrmsr /* Write MTRR base. */
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inc %ecx
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wrmsr /* Write MTRR mask. */
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inc %ecx
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dec %ebx
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jmp 1b
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1:
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/* Get number of MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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2:
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testl %ebx, %ebx
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jz 2f
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/* Low 32 bits of MTRR base. */
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popl %eax
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/* Upper 32 bits of MTRR base. */
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popl %edx
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/* Write MTRR base. */
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wrmsr
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inc %ecx
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/* Low 32 bits of MTRR mask. */
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popl %eax
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/* Upper 32 bits of MTRR mask. */
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popl %edx
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/* Write MTRR mask. */
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wrmsr
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inc %ecx
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dec %ebx
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jmp 2b
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2:
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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post_code(0x3b)
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/* Invalidate the cache again. */
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invd
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post_code(0x3c)
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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call romstage_after_car
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@ -293,3 +189,5 @@ fixed_mtrr_list:
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.word MTRR_FIX_4K_F0000
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.word MTRR_FIX_4K_F8000
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fixed_mtrr_list_size = . - fixed_mtrr_list
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_cache_as_ram_setup_end:
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@ -29,4 +29,5 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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romstage-y += ../car/romstage.c
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@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_I440BX
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select UDELAY_IO
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select POSTCAR_STAGE
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config SDRAMPWR_4DIMM
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bool
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@ -23,4 +23,6 @@ romstage-y += raminit.c
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romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
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romstage-y += ram_calc.c
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postcar-y += ram_calc.c
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endif
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@ -69,9 +69,10 @@ void *cbmem_top(void)
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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@ -91,8 +92,5 @@ void *setup_stack_and_mtrrs(void)
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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run_postcar_phase(&pcf);
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}
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