nb/intel/i440bx: Switch to POSTCAR_STAGE

Boot tested on asus/p2b-ls and p2b-ds.

Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/26821
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-06-04 08:49:17 +03:00
parent 546990710c
commit aea8eecded
5 changed files with 16 additions and 116 deletions

View File

@ -23,6 +23,9 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
.code32
_cache_as_ram_setup:
/* Save the BIST result. */
movl %eax, %ebp
@ -165,118 +168,11 @@ before_romstage:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
/* Disable cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
post_code(0x31)
/* Disable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x32)
invd
post_code(0x33)
/* Enable cache. */
movl %cr0, %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x36)
/* Disable cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
post_code(0x38)
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
clr %eax
clr %edx
1:
testl %ebx, %ebx
jz 1f
wrmsr /* Write MTRR base. */
inc %ecx
wrmsr /* Write MTRR mask. */
inc %ecx
dec %ebx
jmp 1b
1:
/* Get number of MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
2:
testl %ebx, %ebx
jz 2f
/* Low 32 bits of MTRR base. */
popl %eax
/* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
inc %ecx
/* Low 32 bits of MTRR mask. */
popl %eax
/* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
inc %ecx
dec %ebx
jmp 2b
2:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
movl %cr0, %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x3a)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
/* Invalidate the cache again. */
invd
post_code(0x3c)
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
call romstage_after_car
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
@ -293,3 +189,5 @@ fixed_mtrr_list:
.word MTRR_FIX_4K_F0000
.word MTRR_FIX_4K_F8000
fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end:

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@ -29,4 +29,5 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

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@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_I440BX
select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select UDELAY_IO
select POSTCAR_STAGE
config SDRAMPWR_4DIMM
bool

View File

@ -23,4 +23,6 @@ romstage-y += raminit.c
romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
romstage-y += ram_calc.c
postcar-y += ram_calc.c
endif

View File

@ -69,9 +69,10 @@ void *cbmem_top(void)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
void platform_enter_postcar(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
@ -91,8 +92,5 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
/* Save the number of MTRRs to setup. Return the stack location
* pointing to the number of MTRRs.
*/
return postcar_commit_mtrrs(&pcf);
run_postcar_phase(&pcf);
}