asrock/imb-a180: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I5e6e4cabe2b93c41da19412ec3ae2dfaa114bcc0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
a84e34be25
commit
aeadd84e7b
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@ -17,14 +17,13 @@
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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#include "cbfs.h"
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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@ -34,7 +33,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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@ -290,40 +288,16 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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}
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#endif
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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}
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_reset->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
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{
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/* Azalia Controller OEM Cqodec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList;
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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//oem_fan_control(FchParams_env);
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/* XHCI configuration */
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FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* sata configuration */
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -17,7 +17,6 @@ if BOARD_ASROCK_IMB_A180
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select AGESA_LEGACY_WRAPPER
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select CPU_AMD_AGESA_FAMILY16_KB
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select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
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select SOUTHBRIDGE_AMD_AGESA_YANGTZE
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@ -20,7 +20,7 @@
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#include <PlatformMemoryConfiguration.h>
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#include "Filecode.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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@ -104,6 +104,13 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.DdiLinkList = DdiList
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = FALSE;
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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@ -120,7 +127,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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AGESA_STATUS Status;
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PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
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@ -142,14 +149,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
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InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------
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@ -163,7 +162,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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#define SEED_A 0x12
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HW_RXEN_SEED(
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@ -183,7 +182,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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.InitMid = OemInitMid,
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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@ -22,7 +22,7 @@
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#include <device/pci_def.h>
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#include <arch/acpi.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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/**********************************************
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* enable the dedicated function in mainboard.
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@ -30,9 +30,6 @@
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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}
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struct chip_operations mainboard_ops = {
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