sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE. Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode. Many thanks to the people who worked hard on the Asus M2V-MX SE, and all of its components; this vga bringup was a breeze thanks to your hard work for this excellently supported board. And separate thanks to Rudolf Marek for spurring me on and for providing a register dump. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Luc Verhaegen
parent
b2bd9963a5
commit
aeb6c9870f
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@ -44,7 +44,7 @@ uses CONFIG_XIP_ROM_SIZE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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# uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_LB_MEM_TOPK
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uses CONFIG_HAVE_ACPI_TABLES
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uses CONFIG_HAVE_MAINBOARD_RESOURCES
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@ -74,6 +74,7 @@ uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CONFIG_VGA
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
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@ -101,7 +102,7 @@ default CONFIG_HAVE_HARD_RESET = 1
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default CONFIG_HAVE_PIRQ_TABLE = 0
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default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME?
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default CONFIG_HAVE_MP_TABLE = 0
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default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME
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default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME
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# Move the default coreboot CMOS range off of AMD RTC registers.
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default CONFIG_LB_CKS_RANGE_START = 49
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default CONFIG_LB_CKS_RANGE_END = 122
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@ -136,6 +137,7 @@ default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
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# Only offset for SB chain?, default is yes(1).
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default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
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default CONFIG_VGA = 1
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default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
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default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA.
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default CONFIG_USE_DCACHE_RAM = 1
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@ -157,6 +159,7 @@ default CONFIG_HEAP_SIZE = 256 * 1024
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default CONFIG_LB_MEM_TOPK = 32768
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# to 1MB
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default CONFIG_RAMBASE = 0x1F00000
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default CONFIG_USE_OPTION_TABLE = 0
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# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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default CONFIG_ROM_PAYLOAD = 1
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default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
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@ -43,6 +43,7 @@ entries
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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448 3 e 10 videoram_size
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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@ -90,6 +91,13 @@ enumerations
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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# videoram_size: mimics the bits in the ramcontroller.
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10 1 8MB
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10 2 16MB
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10 3 32MB
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10 4 64MB
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10 5 128MB
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10 6 256MB
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checksums
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@ -25,3 +25,4 @@ driver k8t890_host_ctrl.o
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driver k8t890_pcie.o
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driver k8t890_traf_ctrl.o
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driver k8t890_error.o
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driver k8m890_chrome.o
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@ -0,0 +1,179 @@
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/*
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* Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 51
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* Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <string.h> /* for memset */
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#include "k8t890.h"
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#if CONFIG_VGA == 1
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#include <pc80/vga_io.h>
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#include <pc80/vga.h>
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#include <arch/io.h>
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/*
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*
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*/
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static void
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chrome_vga_init(struct device *dev)
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{
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vga_sr_write(0x10, 0x01); /* unlock extended regs */
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vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */
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vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */
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vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */
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/* Make sure that non of the primary VGA overflow registers are set */
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vga_cr_write(0x33, 0x00);
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vga_cr_write(0x35, 0x00);
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vga_cr_mask(0x11, 0x00, 0x30);
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vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */
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vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */
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/* Disable Extended Display Mode */
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vga_sr_mask(0x15, 0x00, 0x02);
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/* Disable Wrap-around */
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vga_sr_mask(0x15, 0x00, 0x20);
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/* Disable Extended Mode memory access */
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vga_sr_mask(0x1A, 0x00, 0x08);
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/* Make sure that we only touch CRTC1s DAC */
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vga_sr_mask(0x1A, 0x00, 0x01);
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/* Set up power to the clocks/crtcs */
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vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */
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vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */
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vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */
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/* set everything according to PM/Engine idle state except pci dma */
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vga_sr_write(0x2D, 0xFF); /* Power management control 1 */
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vga_sr_write(0x2E, 0xFB); /* Power management control 2 */
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vga_sr_write(0x3F, 0xFF); /* Power management control 3 */
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/* now set up the engine clock. */
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vga_sr_write(0x47, 0xB8);
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vga_sr_write(0x48, 0x08);
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vga_sr_write(0x49, 0x03);
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/* trigger engine clock setting */
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vga_sr_mask(0x40, 0x01, 0x01);
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vga_sr_mask(0x40, 0, 0x01);
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vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */
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vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */
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/* Power now indicators... */
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vga_cr_write(0x41, 0xB9);
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vga_cr_write(0x42, 0xB4);
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/* could these be the CRTC2 power now indicators? */
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vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */
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vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */
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/* primary fifo setting */
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vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */
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vga_sr_write(0x17, 0x60); /* max depth: 194 */
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vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */
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vga_sr_write(0x1C, 0x54); /* Fetch count */
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vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */
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vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */
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vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */
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/* Typical Arbiter Control */
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vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */
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vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */
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vga_sr_write(0x50, 0x1F); /* AGP Control Register */
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vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */
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vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */
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}
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#endif /* CONFIG_VGA */
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/*
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*
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*/
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static void
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chrome_init(struct device *dev)
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{
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uint32_t fb_size, fb_address;
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fb_size = k8m890_host_fb_size_get();
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if (!fb_size) {
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printk_warning("Chrome: Device has not been initialised in the"
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" ramcontroller!\n");
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return;
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}
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fb_address = pci_read_config32(dev, 0x10);
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fb_address &= ~0x0F;
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if (!fb_address) {
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printk_warning("Chrome: No FB BAR assigned!\n");
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return;
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}
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printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n",
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fb_size, fb_address);
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//k8m890_host_fb_direct_set(fb_address);
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#if CONFIG_VGA == 1
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/* Now set up the VGA console */
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vga_io_init(); /* Enable full IO access */
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chrome_vga_init(dev);
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vga_textmode_init();
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#if CONFIG_CONSOLE_VGA == 1
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vga_console_init();
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#endif
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printk_info("Chrome VGA Textmode initialized.\n");
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#if CONFIG_CONSOLE_VGA == 0
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/* if we don't have console, at least print something... */
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vga_line_write(0, "Chrome VGA Textmode initialized.");
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#endif
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#endif /* CONFIG_VGA */
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}
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static struct device_operations
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chrome_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = chrome_init,
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.scan_bus = 0,
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.enable = 0,
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};
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static const struct pci_driver unichrome_driver __pci_driver = {
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.ops = &chrome_ops,
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.vendor = 0x1106,
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.device = 0x3230,
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};
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@ -43,4 +43,7 @@
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extern void writeback(struct device *dev, u16 where, u8 what);
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extern void dump_south(device_t dev);
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int k8m890_host_fb_size_get(void);
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//void k8m890_host_fb_direct_set(uint32_t fb_address);
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#endif
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@ -23,6 +23,7 @@
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <pc80/mc146818rtc.h>
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#include <bitops.h>
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#include "k8t890.h"
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@ -104,18 +105,52 @@ extern uint64_t high_tables_base, high_tables_size;
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#endif
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}
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/*
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*
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*/
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int
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k8m890_host_fb_size_get(void)
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{
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struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
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unsigned char tmp;
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tmp = pci_read_config8(dev, 0xA1);
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tmp >>= 4;
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if (tmp & 0x08)
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return 4 << (tmp & 7);
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else
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return 0;
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}
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static void dram_init_fb(struct device *dev)
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{
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/* Important bits:
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* Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
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* bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
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* bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
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* bits 3:0 BASE [31:28]
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* reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
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*/
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u8 tmp;
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uint64_t proposed_base;
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unsigned int fbsize = (K8M890_FBSIZEMB * 1024 * 1024);
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unsigned int fbbits = 0;
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unsigned int fbsize;
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int ret;
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ret = get_option(&fbbits, "videoram_size");
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if (ret) {
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printk_warning("Failed to get videoram size (error %d), using default.\n", ret);
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fbbits = 5;
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}
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if ((fbbits < 1) || (fbbits > 7)) {
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printk_warning("Invalid videoram size (%d), using default.\n",
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4 << fbbits);
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fbbits = 5;
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}
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fbsize = 4 << (fbbits + 20);
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resmax = NULL;
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search_global_resources(
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@ -131,13 +166,13 @@ static void dram_init_fb(struct device *dev)
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proposed_base = resmax->base + resmax->size - fbsize;
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resmax->size -= fbsize;
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printk_debug("VIA FB proposed base: %llx\n", proposed_base);
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printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
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/* Step 1: enable UMA but no FB */
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pci_write_config8(dev, 0xa1, 0x80);
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/* Step 2: enough is just the FB size, the CPU accessible address is not needed */
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tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80;
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tmp = (fbbits << 4) | 0x80;
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pci_write_config8(dev, 0xa1, tmp);
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/* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
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