binaryPI: Clean leftover romstage prototype

Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-11-29 06:37:52 +02:00
parent 34ac1ab4a3
commit aeb85d53e9
7 changed files with 7 additions and 14 deletions

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@ -3,8 +3,6 @@
#include <arch/cpu.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void *asmlinkage romstage_main(unsigned long bist);
#endif

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@ -19,11 +19,10 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/pi/hudson/hudson.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
static void romstage_main_template(void)
{
u32 val;

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@ -19,13 +19,13 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ u32 val;
static void romstage_main_template(void)
{
u32 val;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for

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@ -19,7 +19,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/common/amd_defs.h>
@ -28,7 +27,7 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
static void romstage_main_template(void)
{
u32 val;

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@ -19,12 +19,11 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
static void romstage_main_template(void)
{
u32 val;

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@ -19,7 +19,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@ -28,7 +27,7 @@
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
static void romstage_main_template(void)
{
u32 val;

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@ -21,7 +21,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>