binaryPI: Clean leftover romstage prototype
Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3,8 +3,6 @@
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#include <arch/cpu.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
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void *asmlinkage romstage_main(unsigned long bist);
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#endif
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@ -19,11 +19,10 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/bist.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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static void romstage_main_template(void)
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{
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u32 val;
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@ -19,13 +19,13 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{ u32 val;
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static void romstage_main_template(void)
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{
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u32 val;
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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@ -19,7 +19,6 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/common/amd_defs.h>
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@ -28,7 +27,7 @@
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#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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static void romstage_main_template(void)
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{
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u32 val;
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@ -19,12 +19,11 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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static void romstage_main_template(void)
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{
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u32 val;
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@ -19,7 +19,6 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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static void romstage_main_template(void)
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{
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u32 val;
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@ -21,7 +21,6 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <cpu/x86/bist.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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