binaryPI: Clean leftover romstage prototype

Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/cpu/amd/car.h

@@ -3,8 +3,6 @@
 
 #include <arch/cpu.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
 void *asmlinkage romstage_main(unsigned long bist);
 
 #endif

src/mainboard/amd/bettong/romstage.c

@@ -19,11 +19,10 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 

src/mainboard/amd/db-ft3b-lc/romstage.c

@@ -19,13 +19,13 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
-{	u32 val;
+{
+	u32 val;
 
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for

src/mainboard/amd/lamar/romstage.c

@@ -19,7 +19,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/common/amd_defs.h>
@@ -28,7 +27,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 

src/mainboard/amd/olivehillplus/romstage.c

@@ -19,12 +19,11 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 

src/mainboard/bap/ode_e21XX/romstage.c

@@ -19,7 +19,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,7 +27,7 @@
 
 #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 

src/mainboard/pcengines/apu2/romstage.c

@@ -21,7 +21,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>