From aec294a71ac3bf9438a7c43efd519630bd52130b Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 7 Nov 2022 09:18:08 +0100
Subject: [PATCH] include/spd.h: Fix comment module type information

Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/include/spd.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/include/spd.h b/src/include/spd.h
index ca78d9ce98..7a6e5ab7e0 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -201,7 +201,7 @@ enum spd_memory_type {
 #define SPD_ECC_8BIT (1<<3)
 #define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
 
-/* Byte 3: Module type information */
+/* Byte 20 [5:0]: DDR2 Module type information */
 enum ddr2_module_type {
 	DDR2_SPD_RDIMM = 0x01,
 	DDR2_SPD_UDIMM = 0x02,
@@ -213,6 +213,7 @@ enum ddr2_module_type {
 	DDR2_SPD_MINI_UDIMM = 0x20,
 };
 
+/* Byte 3 [3:0]: DDR3 Module type information */
 enum ddr3_module_type {
 	DDR3_SPD_RDIMM = 0x01,
 	DDR3_SPD_UDIMM = 0x02,
@@ -229,6 +230,7 @@ enum ddr3_module_type {
 	DDR3_SPD_32B_SO_RDIMM = 0x0d,
 };
 
+/* Byte 3 [3:0]: DDR4 Module type information */
 enum ddr4_module_type {
 	DDR4_SPD_RDIMM = 0x01,
 	DDR4_SPD_UDIMM = 0x02,