soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -9,6 +9,10 @@ config CACHE_MRC_SETTINGS
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bool "Save cached MRC settings"
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bool "Save cached MRC settings"
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default n
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default n
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config SOC_INTEL_COMMON_SPI_PROTECT
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bool
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default n
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if CACHE_MRC_SETTINGS
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if CACHE_MRC_SETTINGS
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config MRC_SETTINGS_CACHE_BASE
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config MRC_SETTINGS_CACHE_BASE
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@ -19,6 +19,7 @@ postcar-y += util.c
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ramstage-y += hda_verb.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
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ramstage-y += util.c
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ramstage-y += util.c
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@ -20,9 +20,9 @@
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#include <string.h>
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#include <string.h>
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#include <spi-generic.h>
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include <spi_flash.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "nvm.h"
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#include "nvm.h"
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#include "spi.h"
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/* This module assumes the flash is memory mapped just below 4GiB in the
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/* This module assumes the flash is memory mapped just below 4GiB in the
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* address space for reading. Also this module assumes an area it erased
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* address space for reading. Also this module assumes an area it erased
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@ -0,0 +1,66 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include "spi.h"
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/*
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* Protect range of SPI flash defined by [start, start+size-1] using Flash
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* Protected Range (FPR) register if available.
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*/
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int spi_flash_protect(u32 start, u32 size)
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{
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struct fpr_info fpr_info;
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u32 end = start + size - 1;
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u32 reg;
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int fpr;
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uintptr_t fpr_base;
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if (spi_get_fpr_info(&fpr_info) == -1) {
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printk(BIOS_ERR, "ERROR: FPR Info not found!\n");
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return -1;
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}
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fpr_base = fpr_info.base;
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/* Find first empty FPR */
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for (fpr = 0; fpr < fpr_info.max; fpr++) {
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reg = read32((void *)fpr_base);
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if (reg == 0)
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break;
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fpr_base += sizeof(uint32_t);
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}
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if (fpr >= fpr_info.max) {
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printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
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return -1;
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}
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/* Set protected range base and limit */
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reg = SPI_FPR(start, end) | SPI_FPR_WPE;
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/* Set the FPR register and verify it is protected */
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write32((void *)fpr_base, reg);
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reg = read32((void *)fpr_base);
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if (!(reg & SPI_FPR_WPE)) {
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printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
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return -1;
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}
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printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n",
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__func__, fpr, start, end);
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return 0;
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}
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@ -0,0 +1,45 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SPI_FPR_SHIFT 12
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#define SPI_FPR_MASK 0x7fff
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#define SPI_FPR_BASE_SHIFT 0
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#define SPI_FPR_LIMIT_SHIFT 16
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#define SPI_FPR_RPE (1 << 15) /* Read Protect */
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#define SPI_FPR_WPE (1 << 31) /* Write Protect */
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#define SPI_FPR(base, limit) \
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(((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\
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((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT))
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struct fpr_info {
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/* Offset of first FPR register */
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uintptr_t base;
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/* Maximum number of FPR registers */
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uint8_t max;
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};
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/*
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* SoC is expected to implement this function to provide address of first FPR
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* register and max count of FPR registers.
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*
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* On success return 0 else -1.
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*/
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int spi_get_fpr_info(struct fpr_info *info);
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/*
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* Protect range of SPI flash defined by [start, start+size-1] using Flash
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* Protected Range (FPR) register if available.
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*/
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int spi_flash_protect(u32 start, u32 size);
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