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superio/ite/it8772f: Depreciate early wdt functions 

We have better written generic implementations of these functions
introduced in commit:

 a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5901
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-06-01 20:30:28 +10:00 committed by Kyösti Mälkki
parent 1b3acb13e4
commit aef5594f74
2 changed files with 2 additions and 31 deletions
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30
src/superio/ite/it8772f/early_serial.c
View File

@ -25,16 +25,14 @@
/* NOTICE: This file is deprecated, use ite/common instead */
/* The base address is 0x2e or 0x4e, depending on config bytes. */
#define SIO_BASE IT8772F_BASE
/* FIXME: SUPERIO include.c */
#define SIO_BASE 0x2e
#define SIO_INDEX SIO_BASE
#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */
#define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
u8 it8772f_sio_read(u8 index)
{
@ -63,30 +61,6 @@ static void it8772f_exit_conf(void)
it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz is the default). */
void it8772f_24mhz_clkin(void)
{
it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00);
it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1);
it8772f_exit_conf();
}
/*
* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
*
* Enable 3VSBSW#. (For System Suspend-to-RAM)
* 0: 3VSBSW# will be always inactive.
* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
*/
void it8772f_enable_3vsbsw(void)
{
it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80);
it8772f_exit_conf();
}
/* Set AC resume to be up to the Southbridge */
void it8772f_ac_resume_southbridge(void)
{

3
src/superio/ite/it8772f/it8772f.h
View File

@ -21,9 +21,6 @@
#ifndef SUPERIO_ITE_IT8772F_H
#define SUPERIO_ITE_IT8772F_H
/* FIXME: SUPERIO include.c */
#define IT8772F_BASE 0x2e
#define IT8772F_FDC 0x00 /* Floppy disk controller */
#define IT8772F_SP1 0x01 /* Com1 */
#define IT8772F_EC 0x04 /* Environment controller */