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mb/amd/birman/devicetree_phoenix: update USB PHY settings 

Update the initial USB PHY tuning values that were a copy of the ones
from the Chausie mainboard to the values used in the Birman UEFI
firmware reference implementation. The USB3 PHY tuning values are still
the same while some of the USB2 PHY tuning values are different. The
last two USB2 PHYs that are used by the USB4 controllers have a
different parameter set compared to the other USB2 PHYs.

TEST=All USB ports on Birman function as expected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-06-14 23:58:19 +02:00
parent 42f7dc7493
commit aef7007b0c
1 changed files with 40 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
src/mainboard/amd/birman/devicetree_phoenix.cb
View File

@ -44,13 +44,13 @@ chip soc/amd/phoenix
register "usb_phy_custom" = "1" register "usb_phy_custom" = "1"
register "usb_phy" = "{ register "usb_phy" = "{
.Usb2PhyPort[0] = { .Usb2PhyPort[0] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -58,13 +58,13 @@ chip soc/amd/phoenix
.txrestune = 0x2, .txrestune = 0x2,
}, },
.Usb2PhyPort[1] = { .Usb2PhyPort[1] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -72,13 +72,13 @@ chip soc/amd/phoenix
.txrestune = 0x2, .txrestune = 0x2,
}, },
.Usb2PhyPort[2] = { .Usb2PhyPort[2] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -86,13 +86,13 @@ chip soc/amd/phoenix
.txrestune = 0x2, .txrestune = 0x2,
}, },
.Usb2PhyPort[3] = { .Usb2PhyPort[3] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -100,13 +100,13 @@ chip soc/amd/phoenix
.txrestune = 0x2, .txrestune = 0x2,
}, },
.Usb2PhyPort[4] = { .Usb2PhyPort[4] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -114,13 +114,13 @@ chip soc/amd/phoenix
.txrestune = 0x2, .txrestune = 0x2,
}, },
.Usb2PhyPort[5] = { .Usb2PhyPort[5] = {
.compdistune = 0x3, .compdistune = 0x1,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x3,
@ -131,13 +131,13 @@ chip soc/amd/phoenix
.compdistune = 0x3, .compdistune = 0x3,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x6,
.txhsxvtune = 0x3, .txhsxvtune = 0x3,
.txrestune = 0x2, .txrestune = 0x2,
}, },
@ -145,13 +145,13 @@ chip soc/amd/phoenix
.compdistune = 0x3, .compdistune = 0x3,
.pllbtune = 0x1, .pllbtune = 0x1,
.pllitune = 0x0, .pllitune = 0x0,
.pllptune = 0xe, .pllptune = 0xc,
.sqrxtune = 0x3, .sqrxtune = 0x2,
.txfslstune = 0x3, .txfslstune = 0x1,
.txpreempamptune = 0x2, .txpreempamptune = 0x3,
.txpreemppulsetune = 0x0, .txpreemppulsetune = 0x0,
.txrisetune = 0x1, .txrisetune = 0x1,
.txvreftune = 0x3, .txvreftune = 0x6,
.txhsxvtune = 0x3, .txhsxvtune = 0x3,
.txrestune = 0x2, .txrestune = 0x2,
}, },