skylake: fix SMI GPI status handling
The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
parent
13e2ed3f0c
commit
af030503e8
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@ -17,6 +17,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <gpio.h>
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@ -57,6 +58,36 @@ static const struct gpio_community communities[] = {
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},
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};
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static const char *gpio_group_names[GPIO_NUM_GROUPS] = {
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"GPP_A",
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"GPP_B",
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"GPP_C",
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"GPP_D",
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"GPP_E",
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"GPP_F",
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"GPP_G",
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"GPD",
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};
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static inline size_t gpios_in_community(const struct gpio_community *comm)
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{
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/* max is inclusive */
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return comm->max - comm->min + 1;
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}
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static inline size_t groups_in_community(const struct gpio_community *comm)
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{
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size_t n = gpios_in_community(comm) + GPIO_MAX_NUM_PER_GROUP - 1;
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return n / GPIO_MAX_NUM_PER_GROUP;
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}
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static inline int gpio_index_gpd(gpio_t gpio)
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{
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if (gpio >= GPD0 && gpio <= GPD11)
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return 1;
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return 0;
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}
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static const struct gpio_community *gpio_get_community(gpio_t pad)
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{
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size_t i;
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@ -71,6 +102,90 @@ static const struct gpio_community *gpio_get_community(gpio_t pad)
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return NULL;
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}
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static size_t community_clr_get_smi_sts(const struct gpio_community *comm,
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uint32_t *sts)
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{
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uint8_t *regs;
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size_t i;
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uint32_t *gpi_status_reg;
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uint32_t *gpi_en_reg;
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const size_t num_grps = groups_in_community(comm);
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/* Not all groups can be routed to SMI. However, the registers
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* read as 0. In order to simplify the logic read everything from
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* each community. */
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regs = pcr_port_regs(comm->port_id);
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gpi_status_reg = (void *)®s[GPI_SMI_STS_OFFSET];
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gpi_en_reg = (void *)®s[GPI_SMI_EN_OFFSET];
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for (i = 0; i < num_grps; i++) {
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sts[i] = read32(gpi_status_reg + i) & read32(gpi_en_reg + i);
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/* Clear the enabled and set status bits. */
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write32(gpi_status_reg + i, sts[i]);
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}
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return num_grps;
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}
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static void print_gpi_status(uint32_t status, const char *grp_name)
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{
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int i;
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if (!status)
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return;
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i))
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printk(BIOS_DEBUG, "%s%d ", grp_name, i);
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}
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}
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void gpi_clear_get_smi_status(struct gpi_status *sts)
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{
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int i;
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int do_print;
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size_t sts_index = 0;
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for (i = 0; i < ARRAY_SIZE(communities); i++) {
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const struct gpio_community *comm = &communities[i];
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sts_index += community_clr_get_smi_sts(comm,
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&sts->grp[sts_index]);
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}
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do_print = 0;
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for (i = 0; i < ARRAY_SIZE(sts->grp); i++) {
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if (sts->grp[i] == 0)
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continue;
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do_print = 1;
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break;
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}
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if (!do_print)
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return;
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printk(BIOS_DEBUG, "GPI_SMI_STS: ");
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for (i = 0; i < ARRAY_SIZE(sts->grp); i++)
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print_gpi_status(sts->grp[i], gpio_group_names[i]);
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printk(BIOS_DEBUG, "\n");
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}
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int gpi_status_get(const struct gpi_status *sts, gpio_t gpi)
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{
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const uint32_t *gpi_sts;
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/* Check if valid gpi */
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if (gpio_get_community(gpi) == NULL)
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return 0;
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/* If not in GPD group the index is a linear function based on
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* GPI number and GPIO_MAX_NUM_PER_GROUP. */
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if (gpio_index_gpd(gpi))
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gpi_sts = &sts->grp[GPD];
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else
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gpi_sts = &sts->grp[gpi / GPIO_MAX_NUM_PER_GROUP];
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return !!(*gpi_sts & (1 << (gpi % GPIO_MAX_NUM_PER_GROUP)));
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}
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void gpio_route_gpe(uint16_t gpe0_route)
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{
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int i;
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@ -272,133 +387,3 @@ void gpio_set(gpio_t gpio_num, int value)
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write32(&dw_regs[0], reg);
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/* GPIO port ids support posted write semantics. */
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}
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/* Keep the ordering intact GPP_A ~ G, GPD.
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* As the gpio/smi functions gpio_get_smi_status() and
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* gpio_enable_groupsmi() depends on this ordering.
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*/
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static const GPIO_GROUP_INFO gpio_group_info[] = {
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/* GPP_A */
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{
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.community = PID_GPIOCOM0,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_A_PAD_MAX,
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.smistsoffset = R_PCH_PCR_GPIO_GPP_A_SMI_STS,
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.smienoffset = R_PCH_PCR_GPIO_GPP_A_SMI_EN,
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},
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/* GPP_B */
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{
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.community = PID_GPIOCOM0,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_B_PAD_MAX,
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.smistsoffset = R_PCH_PCR_GPIO_GPP_B_SMI_STS,
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.smienoffset = R_PCH_PCR_GPIO_GPP_B_SMI_EN,
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},
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/* GPP_C */
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{
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.community = PID_GPIOCOM1,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_C_PAD_MAX,
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.smistsoffset = R_PCH_PCR_GPIO_GPP_C_SMI_STS,
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.smienoffset = R_PCH_PCR_GPIO_GPP_C_SMI_EN,
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},
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/* GPP_D */
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{
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.community = PID_GPIOCOM1,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_D_PAD_MAX,
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.smistsoffset = R_PCH_PCR_GPIO_GPP_D_SMI_STS,
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.smienoffset = R_PCH_PCR_GPIO_GPP_D_SMI_EN,
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},
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/* GPP_E */
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{
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.community = PID_GPIOCOM1,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_E_PAD_MAX,
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.smistsoffset = R_PCH_PCR_GPIO_GPP_E_SMI_STS,
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.smienoffset = R_PCH_PCR_GPIO_GPP_E_SMI_EN,
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},
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/* GPP_F */
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{
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.community = PID_GPIOCOM3,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_F_PAD_MAX,
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.smistsoffset = NO_REGISTER_PROPERTY,
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.smienoffset = NO_REGISTER_PROPERTY,
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},
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/* GPP_G */
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{
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.community = PID_GPIOCOM3,
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.padcfgoffset = R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPP_G_PAD_MAX,
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.smistsoffset = NO_REGISTER_PROPERTY,
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.smienoffset = NO_REGISTER_PROPERTY,
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},
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/* GPD */
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{
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.community = PID_GPIOCOM2,
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.padcfgoffset = R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET,
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.padpergroup = V_PCH_GPIO_GPD_PAD_MAX,
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.smistsoffset = NO_REGISTER_PROPERTY,
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.smienoffset = NO_REGISTER_PROPERTY,
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},
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};
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void gpio_clear_all_smi(void)
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{
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u32 gpiogroupinfolength;
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u32 gpioindex = 0;
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gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO);
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for (gpioindex = 0; gpioindex < gpiogroupinfolength; gpioindex++) {
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/*Check if group has GPI SMI register */
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if (gpio_group_info[gpioindex].smistsoffset ==
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NO_REGISTER_PROPERTY)
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continue;
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/* Clear all GPI SMI Status bits by writing '1' */
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pcr_write32(gpio_group_info[gpioindex].community,
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gpio_group_info[gpioindex].smistsoffset,
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0xFFFFFFFF);
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}
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}
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void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX])
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{
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u32 num_of_communities;
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u32 gpioindex;
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u32 outputvalue = 0;
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num_of_communities = ARRAY_SIZE(gpio_group_info);
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for (gpioindex = 0; gpioindex < num_of_communities; gpioindex++) {
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/*Check if group has GPI SMI register */
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if (gpio_group_info[gpioindex].smistsoffset ==
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NO_REGISTER_PROPERTY)
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continue;
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/* Read SMI status register */
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pcr_read32(gpio_group_info[gpioindex].community,
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gpio_group_info[gpioindex].smistsoffset,
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&outputvalue);
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status[gpioindex] = outputvalue;
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}
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}
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void gpio_enable_all_smi(void)
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{
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u32 gpiogroupinfolength;
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u32 gpioindex = 0;
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gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO);
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for (gpioindex = 0; gpioindex < gpiogroupinfolength; gpioindex++) {
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/*Check if group has GPI SMI register */
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if (gpio_group_info[gpioindex].smienoffset ==
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NO_REGISTER_PROPERTY)
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continue;
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/* Set all GPI SMI Enable bits by writing '1' */
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pcr_write32(gpio_group_info[gpioindex].community,
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gpio_group_info[gpioindex].smienoffset,
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0xFFFFFFFF);
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}
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}
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@ -28,19 +28,22 @@
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#include <stddef.h>
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#include <soc/gpio_fsp.h>
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/* SOC has 8 GPIO communities GPP A~G, GPD */
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#define GPIO_COMMUNITY_MAX 8
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typedef uint32_t gpio_t;
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/* Clear GPIO SMI Status */
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void gpio_clear_all_smi(void);
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/* Structure to represent GPI status for GPE and SMI. Use helper
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* functions for interrogating particular GPIs. */
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struct gpi_status {
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uint32_t grp[GPIO_NUM_GROUPS];
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};
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/* Get GPIO SMI Status */
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void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]);
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/*
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* Clear GPI SMI status and fill in the structure representing enabled
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* and set status.
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*/
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void gpi_clear_get_smi_status(struct gpi_status *sts);
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/* Enable GPIO SMI */
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void gpio_enable_all_smi(void);
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/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
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int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
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/*
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* Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted
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@ -174,10 +174,6 @@ uint32_t clear_smi_status(void);
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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/* ALT_GP_SMI */
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uint32_t clear_alt_smi_status(void);
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void reset_alt_smi_status(void);
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/* TCO */
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uint32_t clear_tco_status(void);
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void enable_tco_sci(void);
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@ -25,6 +25,7 @@
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#include <cpu/x86/msr.h>
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#include <soc/intel/common/romstage.h>
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#include <soc/intel/common/memmap.h>
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#include <soc/gpio.h>
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struct ied_header {
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char signature[10];
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@ -51,6 +52,10 @@ struct smm_relocation_params {
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int smm_save_state_in_msrs;
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};
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/* Mainboard handler for GPI SMIs*/
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void mainboard_smi_gpi_handler(const struct gpi_status *sts);
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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int smm_initialize(void);
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void smm_relocate(void);
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@ -210,54 +210,6 @@ void disable_smi(u32 mask)
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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}
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/*
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* ALT_GP_SMI
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*/
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/* Clear GPIO SMI status and return events that are enabled and active */
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void reset_alt_smi_status(void)
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{
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/*Clear GPIO SMI Status*/
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gpio_clear_all_smi();
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}
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/* Print GPIO SMI status bits */
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static u32 print_alt_smi_status(void)
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{
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u32 alt_sts[GPIO_COMMUNITY_MAX];
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int gpio_index;
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/* GPIO Communities GPP_A ~ E support SMI */
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const char gpiowell[] = {
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[0] = 'A',
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[1] = 'B',
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[2] = 'C',
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[3] = 'D',
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[4] = 'E'
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};
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printk(BIOS_DEBUG, "ALT_STS: ");
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gpio_get_smi_status(alt_sts);
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/* GPP_A to GPP_E GPIO has Status and Enable functionality*/
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for (gpio_index = 0; gpio_index < ARRAY_SIZE(gpiowell);
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gpio_index++) {
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printk(BIOS_DEBUG, "GPIO Group_%c\n",
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gpiowell[gpio_index]);
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print_gpio_status(alt_sts[gpio_index], 0);
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}
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printk(BIOS_DEBUG, "\n");
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return 0;
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}
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/* Print, clear, and return GPIO SMI status */
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u32 clear_alt_smi_status(void)
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{
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reset_alt_smi_status();
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return print_alt_smi_status();
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}
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/*
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* TCO
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*/
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@ -351,12 +351,18 @@ static void southbridge_smi_gpe0(void)
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clear_gpe_status();
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}
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void __attribute__((weak))
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mainboard_smi_gpi_handler(const struct gpi_status *sts) { }
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static void southbridge_smi_gpi(void)
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{
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mainboard_smi_gpi(clear_alt_smi_status());
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struct gpi_status smi_sts;
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gpi_clear_get_smi_status(&smi_sts);
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mainboard_smi_gpi_handler(&smi_sts);
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/* Clear again after mainboard handler */
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clear_alt_smi_status();
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gpi_clear_get_smi_status(&smi_sts);
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}
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static void southbridge_smi_mc(void)
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