mb/google/brya/var/mithrax: update overridetree and Kconfig
1. Update override devicetree based on schematics. 2. Update Kconfig based on schematics. BUG=b:229191897 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
This commit is contained in:
John Su
Tim Wawrzynczak
parent
31021b3720
commit
af092ac6ec
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@ -122,6 +122,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x1 if BOARD_GOOGLE_CROTA
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default 0x1 if BOARD_GOOGLE_CROTA
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default 0x1 if BOARD_GOOGLE_MOLI
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default 0x1 if BOARD_GOOGLE_MOLI
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default 0x1 if BOARD_GOOGLE_OSIRIS
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default 0x1 if BOARD_GOOGLE_OSIRIS
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default 0x1 if BOARD_GOOGLE_MITHRAX
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config DRIVER_TPM_I2C_ADDR
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config DRIVER_TPM_I2C_ADDR
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hex
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hex
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@ -216,3 +216,5 @@ config BOARD_GOOGLE_OSIRIS
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config BOARD_GOOGLE_MITHRAX
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config BOARD_GOOGLE_MITHRAX
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bool "-> Mithrax"
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bool "-> Mithrax"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENESYSLOGIC_GL9755
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@ -1,6 +1,360 @@
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fw_config
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field DB_USB 0 2
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option USB_ABSENT 0
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option USB3_PS8815 1
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end
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field STYLUS 5
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option STYLUS_ABSENT 0
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option STYLUS_PRESENT 1
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end
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field AUDIO_AMP 7 9
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option UNPROVISIONED 0
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option MAX98360_ALC5682VS_I2S_2WAY 1
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
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# bypass rails implemented.
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY"
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb3_ports[3]" = "USB3_PORT_EMPTY"
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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}"
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# As per Intel Advisory doc#723158, the change is required to prevent possible
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# display flickering issue.
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register "usb2_phy_sus_pg_disable" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | Audio |
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#| I2C1 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C3 | Touchscreen |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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device domain 0 on
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device domain 0 on
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end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM_SOC""
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register "options.tsr[1].desc" = ""Ambient""
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register "options.tsr[2].desc" = ""Charger""
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(48, 76),
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TEMP_PCT(45, 65),
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TEMP_PCT(42, 53),
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TEMP_PCT(39, 45),
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TEMP_PCT(36, 39),
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TEMP_PCT(33, 34),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 70, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_1, 70, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 13000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 28 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 55000,
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.max_power = 55000,
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.time_window_min = 32 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref tcss_dma0 off end
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device ref tcss_dma1 off end
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device ref pcie_rp6 off end
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end #PCIE8 SD card
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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probe AUDIO_AMP MAX98360_ALC5682VS_I2S_2WAY
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end
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end
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end #I2C0
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end #I2C1
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device ref i2c3 on
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN9008""
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "300"
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register "generic.reset_off_delay_ms" = "1"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "6"
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "generic.stop_off_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A7)"
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register "key.wake_gpe" = "GPE0_DW0_08"
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register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
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register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on
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probe STYLUS STYLUS_PRESENT
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end
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end
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end #I2C3
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "probed" = "1"
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device i2c 15 on end
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end
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end #I2C5
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device ref hda on
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chip drivers/generic/max98357a
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register "hid" = ""MX98360A""
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register "sdmode_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn1 as mux_conn[1]
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use conn2 as mux_conn[0]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 2 alias conn2 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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||||||
|
register "desc" = ""USB2 Type-C Port C2 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||||
|
device ref usb2_port3 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Camera""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device ref usb2_port6 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port A0 (DB)""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||||
|
device ref usb2_port9 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
register "reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||||
|
device ref usb2_port10 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port A0 (DB)""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||||
|
device ref usb3_port1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <chip.h>
|
||||||
|
#include <fw_config.h>
|
||||||
|
#include <baseboard/variants.h>
|
||||||
|
|
||||||
|
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||||
|
{
|
||||||
|
if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) {
|
||||||
|
config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19;
|
||||||
|
config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20;
|
||||||
|
config->tcss_aux_ori = 0x10;
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue