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mainboard/google/zoombini/variants/meowth: Fix USB OC settings 

Set USB2 port 0 & 1 to use OC2 and OC3 respectively.  Previous settings
were causing false overcurrent conditions as OC0 and OC1 were used for
other purposes.

Remove initialization of unused usb3 ports, and configure the ports we
use (usb3 ports 0 & 1) to use OC2 and OC3, respectively.

BUG=b:72250084
BRANCH=none
TEST=Verify meowth can recognize and boot off a kernel on USB drive.

Change-Id: I528b67d80a1da84e5307facb40de545089979f57
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nick Vaccaro 2018-01-21 22:14:40 -08:00 committed by Martin Roth
parent 6978971c4a
commit af0e7d18a7
1 changed files with 5 additions and 9 deletions
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14
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
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@ -39,9 +39,9 @@ chip soc/intel/cannonlake
.early_init = 1,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
@ -50,12 +50,8 @@ chip soc/intel/cannonlake
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
device domain 0 on
device pci 00.0 on end # Host Bridge