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qualcomm/sc7280: Add display external clock support in coreboot 

Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Taniya Das 2021-11-19 14:19:18 +05:30 committed by Felix Held
parent e93bce937e
commit af2c89c463
2 changed files with 53 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/qualcomm/sc7280/clock.c
View File

@ -203,20 +203,28 @@ static struct clock_freq_config mdss_mdp_cfg[] = {
},
};
static struct clock_rcg_mnd *mdss_clock[MDSS_CLK_COUNT] = {
[MDSS_CLK_PCLK0] = &mdss->pclk0,
static struct clock_rcg *mdss_clock[MDSS_CLK_COUNT] = {
[MDSS_CLK_MDP] = &mdss->mdp,
[MDSS_CLK_VSYNC] = &mdss->vsync,
[MDSS_CLK_ESC0] = &mdss->esc0,
[MDSS_CLK_BYTE0] = &mdss->byte0,
[MDSS_CLK_BYTE0_INTF] = &mdss->byte0,
[MDSS_CLK_AHB] = &mdss->ahb,
[MDSS_CLK_AHB] = &mdss->mdss_ahb,
[MDSS_CLK_EDP_LINK] = &mdss->edp_link,
[MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link,
[MDSS_CLK_EDP_AUX] = &mdss->edp_aux,
};
static struct clock_rcg_mnd *mdss_clock_mnd[MDSS_CLK_COUNT] = {
[MDSS_CLK_PCLK0] = &mdss->pclk0,
[MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel,
};
static u32 *mdss_cbcr[MDSS_CLK_COUNT] = {
[GCC_DISP_AHB] = &gcc->disp_ahb_cbcr,
[GCC_DISP_HF_AXI] = &gcc->disp_hf_axi_cbcr,
[GCC_DISP_SF_AXI] = &gcc->disp_sf_axi_cbcr,
[GCC_EDP_CLKREF_EN] = &gcc->edp_clkref_en,
[MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr,
[MDSS_CLK_MDP] = &mdss->mdp_cbcr,
[MDSS_CLK_VSYNC] = &mdss->vsync_cbcr,
@ -224,6 +232,10 @@ static u32 *mdss_cbcr[MDSS_CLK_COUNT] = {
[MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr,
[MDSS_CLK_ESC0] = &mdss->esc0_cbcr,
[MDSS_CLK_AHB] = &mdss->ahb_cbcr,
[MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel_cbcr,
[MDSS_CLK_EDP_LINK] = &mdss->edp_link_cbcr,
[MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link_intf_cbcr,
[MDSS_CLK_EDP_AUX] = &mdss->edp_aux_cbcr,
};
static u32 *gdsc[MAX_GDSC] = {
@ -401,8 +413,16 @@ enum cb_err mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz,
mdss_clk_cfg.n = n;
mdss_clk_cfg.d_2 = d_2;
return clock_configure((struct clock_rcg *)mdss_clock[clk_type],
&mdss_clk_cfg, hz, 0);
switch (clk_type) {
case MDSS_CLK_EDP_PIXEL:
case MDSS_CLK_PCLK0:
return clock_configure((struct clock_rcg *)
mdss_clock_mnd[clk_type],
&mdss_clk_cfg, hz, 0);
default:
return clock_configure(mdss_clock[clk_type],
&mdss_clk_cfg, hz, 0);
}
}
enum cb_err mdss_clock_enable(enum clk_mdss clk_type)

38
src/soc/qualcomm/sc7280/include/soc/clock.h
View File

@ -89,23 +89,34 @@ struct sc7280_disp_cc {
u32 esc0_cbcr;
u8 _res3[0x1050 - 0x103c];
u32 ahb_cbcr;
u8 _res4[0x1078 - 0x1054];
u32 edp_pixel_cbcr;
u32 edp_link_cbcr;
u32 edp_link_intf_cbcr;
u32 edp_aux_cbcr;
u8 _res4[0x1078 - 0x1064];
struct clock_rcg_mnd pclk0;
u8 _res5[0x1090 - 0x108c];
struct clock_rcg_mnd mdp;
struct clock_rcg mdp;
u8 _res6[0x10c0 - 0x1098];
struct clock_rcg_mnd vsync;
struct clock_rcg vsync;
u8 _res7[0x10d8 - 0x10c8];
struct clock_rcg_mnd byte0;
u8 _res8[0x10f4 - 0x10ec];
struct clock_rcg_mnd esc0;
u8 _res9[0x1170 - 0x1108];
struct clock_rcg_mnd ahb;
u8 _res10[0x20000 - 0x1178];
struct clock_rcg byte0;
u8 _res8[0x10f4 - 0x10e0];
struct clock_rcg esc0;
u8 _res9[0x1170 - 0x10fc];
struct clock_rcg mdss_ahb;
u8 _res10[0x1188 - 0x1178];
struct clock_rcg_mnd edp_pixel;
u8 _res11[0x11a0 - 0x119c];
struct clock_rcg edp_link;
u8 _res12[0x11d0 - 0x11a8];
struct clock_rcg edp_aux;
u8 _res13[0x20000 - 0x11d8];
};
check_member(sc7280_disp_cc, pclk0_cbcr, 0x1010);
check_member(sc7280_disp_cc, vsync_cbcr, 0x102c);
check_member(sc7280_disp_cc, ahb_cbcr, 0x1050);
check_member(sc7280_disp_cc, edp_aux_cbcr, 0x1060);
struct sc7280_pcie {
u32 pcie_1_bcr;
@ -205,7 +216,8 @@ struct sc7280_gcc {
struct clock_rcg_mnd sdcc1;
u8 _res20[0x8c004 - 0x75020];
u32 pcie_clkref_en;
u8 _res21[0x8d000 - 0x8c008];
u32 edp_clkref_en;
u8 _res21[0x8d000 - 0x8c00c];
struct sc7280_pcie pcie_1;
u8 _res22[0x90010 - 0x8e020];
u32 aggre_noc_pcie_tbu_cbcr;
@ -226,6 +238,7 @@ check_member(sc7280_gcc, apcs_pll_br_en, 0x52010);
check_member(sc7280_gcc, usb_phy_cfg_ahb2phy_bcr, 0x6a000);
check_member(sc7280_gcc, sdcc1_ahb_cbcr, 0x75004);
check_member(sc7280_gcc, pcie_clkref_en, 0x8c004);
check_member(sc7280_gcc, edp_clkref_en, 0x8c008);
check_member(sc7280_gcc, aggre_noc_pcie_tbu_cbcr, 0x90010);
check_member(sc7280_gcc, usb30_sec_bcr, 0x9e000);
@ -293,6 +306,7 @@ enum clk_mdss {
GCC_DISP_AHB,
GCC_DISP_HF_AXI,
GCC_DISP_SF_AXI,
GCC_EDP_CLKREF_EN,
MDSS_CLK_PCLK0,
MDSS_CLK_MDP,
MDSS_CLK_VSYNC,
@ -300,6 +314,10 @@ enum clk_mdss {
MDSS_CLK_BYTE0_INTF,
MDSS_CLK_ESC0,
MDSS_CLK_AHB,
MDSS_CLK_EDP_PIXEL,
MDSS_CLK_EDP_LINK,
MDSS_CLK_EDP_LINK_INTF,
MDSS_CLK_EDP_AUX,
MDSS_CLK_COUNT
};