From af2f8b92974cc698f72fc1e2a1979293611c029f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 10 Jan 2022 10:26:52 +0000 Subject: [PATCH] soc/intel/alderlake: Choose non-posted write to lock GPIO PAD Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake to instruct Pad Configuration Lock to use non-posted sideband writes as posted write is not supported on Alder Lake while locking GPIO pads. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nick Vaccaro Reviewed-by: Maulik V Vaghela Reviewed-by: EricR Lai --- src/soc/intel/alderlake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 74c14a5ef6..04e113a911 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -73,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IPU