From af343cff7671ddf4b03b8d7373849fd74f3f7bf9 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 23 Jun 2021 11:26:10 +0530 Subject: [PATCH] soc/amd/picasso: Allow end range entry for max device ID in IVRS Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel Reviewed-by: Jason Glenesk Reviewed-by: ritul guru Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/agesa_acpi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index abac9c1804..312d5e8cd1 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -21,6 +21,8 @@ #include #include +#define MAX_DEV_ID 0xFFFF + unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -230,7 +232,7 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs) /* Now repeat all the device entries from type 10h */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivhd_40->length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, @@ -304,7 +306,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs) /* Now repeat all the device entries from type 10h */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivhd_11->length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, @@ -442,11 +444,11 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) } /* - * Add all possible PCI devices on bus 0 that can generate transactions + * Add all possible PCI devices that can generate transactions * processed by IOMMU. Start with device 00:01.0 */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivrs->ivhd.length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level,