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mainboard/intel/cannonlake_rvp: enable SD card 

Set SCS SD enable FSP parameter and set card detect
gpio information.

Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Bora Guvendik 2017-09-19 14:15:10 -07:00 committed by Martin Roth
parent 17034d6f63
commit af36f1d525
2 changed files with 8 additions and 0 deletions
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4
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -10,6 +10,7 @@ chip soc/intel/cannonlake
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
@ -70,6 +71,9 @@ chip soc/intel/cannonlake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device

4
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -10,6 +10,7 @@ chip soc/intel/cannonlake
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
@ -68,6 +69,9 @@ chip soc/intel/cannonlake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device