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mb/google/deltaur: Remove WLAN PCIE setting 

Deltaur uses CNVi WLAN module, this setting is not required.

BUG=none
TEST=WiFi is functional in OS.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eric Lai 2020-05-18 12:41:28 +08:00 committed by Patrick Georgi
parent 38c308515c
commit af417b4143
1 changed files with 1 additions and 6 deletions
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7
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
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@ -51,11 +51,6 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[2]" = "USB3_PORT_EMPTY"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# PCIe root port 6 (WLAN), clock 1
register "PcieRpEnable[5]" = "1"
register "PcieClkSrcUsage[1]" = "5"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 7 (Card Reader), clock 4 # PCIe root port 7 (Card Reader), clock 4
register "PcieRpEnable[6]" = "1" register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[4]" = "6" register "PcieClkSrcUsage[4]" = "6"
@ -286,7 +281,7 @@ chip soc/intel/tigerlake
device pci 1c.2 off end # PCIe Root Port #3 () device pci 1c.2 off end # PCIe Root Port #3 ()
device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.3 off end # PCIe Root Port #4 (WWAN)
device pci 1c.4 on end # PCIe Root Port #5 (LTE) device pci 1c.4 on end # PCIe Root Port #5 (LTE)
device pci 1c.5 on end # PCIe Root Port #6 (WiFi) device pci 1c.5 off end # PCIe Root Port #6 (WiFi)
device pci 1c.6 on end # PCIe Root Port #7 (Card reader) device pci 1c.6 on end # PCIe Root Port #7 (Card reader)
device pci 1c.7 on device pci 1c.7 on
chip drivers/net chip drivers/net