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mb/google/brya/var/*: Mark fingerprint reader as hidden 

Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.

TEST=build/boot Win11 on google/brya (kano), verify FPR does not show
up as unknown device under Device Manager.

Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Matt DeVillier 2023-10-28 11:16:14 -05:00 committed by Felix Held
parent 7065ea3487
commit af46b4786f
19 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/variants/anahera/overridetree.cb
View File

@ -327,7 +327,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -309,7 +309,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/brask/overridetree.cb
View File

@ -153,7 +153,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -1065,7 +1065,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/crota/overridetree.cb
View File

@ -322,7 +322,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/gimble/overridetree.cb
View File

@ -261,7 +261,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/gimble4es/overridetree.cb
View File

@ -225,7 +225,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@ -486,7 +486,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/marasov/overridetree.cb
View File

@ -354,7 +354,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -314,7 +314,7 @@ chip soc/intel/alderlake
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
device spi 0 on end
device spi 0 hidden end
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"

2
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -308,7 +308,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/redrix/overridetree.cb
View File

@ -495,7 +495,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/redrix4es/overridetree.cb
View File

@ -494,7 +494,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/skolas/overridetree.cb
View File

@ -989,7 +989,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/skolas4es/overridetree.cb
View File

@ -769,7 +769,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/taeko/overridetree.cb
View File

@ -578,7 +578,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/taeko4es/overridetree.cb
View File

@ -438,7 +438,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@ -433,7 +433,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on

2
src/mainboard/google/brya/variants/zydron/overridetree.cb
View File

@ -464,7 +464,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 on end
device spi 0 hidden end
end # FPMCU
end
device ref pch_espi on