sb/intel: Use `bool` for PCIe coalescing option

Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.

Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/apple/macbookair4_2/devicetree.cb

@@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge
 			register "gen4_dec" = "0x00fc0701"
 			register "gpi7_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x1"
 			device pci 16.0 on # Management Engine Interface 1

src/mainboard/asrock/b75pro3-m/devicetree.cb

@@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x000c0241"
 			register "gen3_dec" = "0x000c0251"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "0"
+			register "pcie_port_coalesce" = "false"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x3f"
 			register "superspeed_capable_ports" = "0x0000000f"

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb

@@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge
 		chip southbridge/intel/bd82x6x
 			register "gen1_dec" = "0x000c0291"
 			register "gen4_dec" = "0x0000ff29"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			device pci 1c.0 on  end	# PCIe Port 1 PCIEX_16_3
 			device pci 1c.1 on  end	# PCIe Port 2 RTL8111F

src/mainboard/compulab/intense_pc/devicetree.cb

@@ -37,7 +37,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx
 			register "gen3_dec" = "0x000406f1"
 			register "gen4_dec" = "0x000c06a1"
 			register "gpi7_routing" = "2"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			# Intense PC SATA portmap:
 			# Port 0: internal 2.5" bay

src/mainboard/dell/optiplex_9010/devicetree.cb

@@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x007c0901"
 			register "gen3_dec" = "0x003c07e1"
 			register "gen4_dec" = "0x001c0901"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x7"
 			register "spi_lvscc" = "0x2005"

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -33,7 +33,7 @@ chip soc/intel/broadwell
 			register "pcie_port_force_aspm" = "0x10"
 
 			# Enable port coalescing
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x01220000"

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -36,7 +36,7 @@ chip soc/intel/broadwell
 
 			# Force enable ASPM for PCIe Port 3
 			register "pcie_port_force_aspm" = "0x04"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x013b0000"

src/mainboard/google/beltino/devicetree.cb

@@ -44,7 +44,7 @@ chip northbridge/intel/haswell
 			register "pcie_port_force_aspm" = "0x10"
 
 			# Enable port coalescing
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x01220000"

src/mainboard/google/butterfly/devicetree.cb

@@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x00040381"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1

src/mainboard/google/jecht/devicetree.cb

@@ -38,7 +38,7 @@ chip soc/intel/broadwell
 			register "pcie_port_force_aspm" = "0x10"
 
 			# Enable port coalescing
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x01220000"

src/mainboard/google/link/devicetree.cb

@@ -56,7 +56,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x00fc0901"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2

src/mainboard/google/parrot/devicetree.cb

@@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x00040069"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2

src/mainboard/google/stout/devicetree.cb

@@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge
 			register "gen3_dec" = "0x0001C1611"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1

src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb

@@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge
 			register "gen1_dec" = "0x00fc0601"
 			register "gen2_dec" = "0x00fc0801"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0xf"
 			register "spi_lvscc" = "0x2005"

src/mainboard/hp/snb_ivb_laptops/devicetree.cb

@@ -29,7 +29,7 @@ chip northbridge/intel/sandybridge
 		device pci 00.0 on  end	# Host bridge
 
 		chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0"

src/mainboard/hp/z220_sff_workstation/devicetree.cb

@@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge
 			register "gen1_dec" = "0x00fc0601"
 			register "gen2_dec" = "0x00fc0801"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0xf"
 			register "spi_lvscc" = "0x2005"

src/mainboard/kontron/ktqm77/devicetree.cb

@@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge
 			#register "gen4_dec" = "0x00000000"
 
 			# Disable root port coalescing
-			register "pcie_port_coalesce" = "0"
+			register "pcie_port_coalesce" = "false"
 
 			register "xhci_switchable_ports"	= "0x0f"
 			register "superspeed_capable_ports"	= "0x0f"

src/mainboard/lenovo/l520/devicetree.cb

@@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi6_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x3b"
 

src/mainboard/lenovo/s230u/devicetree.cb

@@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi7_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x5"
 			register "superspeed_capable_ports" = "0x0000000f"

src/mainboard/lenovo/t420/devicetree.cb

@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# device specific SPI configuration
 			register "spi_uvscc" = "0x2005"

src/mainboard/lenovo/t420s/devicetree.cb

@@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			# device specific SPI configuration
 			register "spi_uvscc" = "0x2005"

src/mainboard/lenovo/t430/devicetree.cb

@@ -35,7 +35,7 @@ chip northbridge/intel/sandybridge
 			register "gpi13_routing" = "2"
 			register "gpi1_routing" = "2"
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x17"
 			register "superspeed_capable_ports" = "0x0000000f"

src/mainboard/lenovo/t430s/devicetree.cb

@@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "docking_supported" = "1"
 
 			register "spi_uvscc" = "0x2005"

src/mainboard/lenovo/t520/devicetree.cb

@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "gen4_dec" = "0x0c06a1"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 

src/mainboard/lenovo/t530/devicetree.cb

@@ -52,7 +52,7 @@ chip northbridge/intel/sandybridge
 			register "gen4_dec" = "0x0c06a1"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
 

src/mainboard/lenovo/x131e/devicetree.cb

@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x00000c03"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"

src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb

@@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"

src/mainboard/lenovo/x220/devicetree.cb

@@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"

src/mainboard/lenovo/x230/devicetree.cb

@@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge
 			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 
 			register "spi_uvscc" = "0x2005"
 			register "spi_lvscc" = "0x2005"

src/mainboard/msi/ms7707/devicetree.cb

@@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge
 			register "docking_supported" = "0"
 			register "gen1_dec" = "0x000c0291"
 			register "gen2_dec" = "0x000c0a01"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x33"
 			register "spi_lvscc" = "0x2005"

src/mainboard/roda/rv11/variants/rv11/devicetree.cb

@@ -46,7 +46,7 @@ chip northbridge/intel/sandybridge
 			register "gpe0_en" = "0x00800040"
 
 			# Disable root port coalescing
-			register "pcie_port_coalesce" = "0"
+			register "pcie_port_coalesce" = "false"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
 

src/mainboard/roda/rv11/variants/rw11/devicetree.cb

@@ -51,7 +51,7 @@ chip northbridge/intel/sandybridge
 			register "gpe0_en" = "0x00800040"
 
 			# Disable root port coalescing
-			register "pcie_port_coalesce" = "0"
+			register "pcie_port_coalesce" = "false"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
 
 

src/mainboard/sapphire/pureplatinumh61/devicetree.cb

@@ -14,7 +14,7 @@ chip northbridge/intel/sandybridge
 		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
 			register "gen1_dec" = "0x000c0291"
 			register "gen2_dec" = "0x000c0a01"
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x33"
 			register "spi.opprefixes" = "{ 0x50, 0x06 }"

src/mainboard/supermicro/x9scl/devicetree.cb

@@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff)
 			register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3)
 			register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff)
-			register "pcie_port_coalesce" = "1"
+			register "pcie_port_coalesce" = "true"
 			register "sata_interface_speed_support" = "0x3"
 			register "sata_port_map" = "0x3f"
 			register "spi_lvscc" = "0x2005"

src/soc/intel/broadwell/pch/chip.h

@@ -3,7 +3,7 @@
 #ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_
 #define _SOC_INTEL_BROADWELL_PCH_CHIP_H_
 
-#include <stdint.h>
+#include <types.h>
 
 struct soc_intel_broadwell_pch_config {
 	/* GPE configuration */
@@ -47,7 +47,7 @@ struct soc_intel_broadwell_pch_config {
 	uint32_t gen4_dec;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	/* Force root port ASPM configuration with port bitmap */
 	uint8_t pcie_port_force_aspm;

src/soc/intel/broadwell/pch/pcie.c

@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pciexp.h>
@@ -15,7 +16,7 @@
 #include <soc/intel/broadwell/pch/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <delay.h>
+#include <types.h>
 
 /* Low Power variant has 6 root ports. */
 #define MAX_NUM_ROOT_PORTS 6
@@ -31,7 +32,7 @@ struct root_port_config {
 	u32 b0d28f0_32c;
 	u32 b0d28f4_32c;
 	u32 b0d28f5_32c;
-	int coalesce;
+	bool coalesce;
 	int gbe_port;
 	int num_ports;
 	struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -274,7 +275,7 @@ static void root_port_commit_config(void)
 
 	/* If the first root port is disabled the coalesce ports. */
 	if (!rpc.ports[0]->enabled)
-		rpc.coalesce = 1;
+		rpc.coalesce = true;
 
 	/* Perform clock gating configuration. */
 	pcie_enable_clock_gating();

src/southbridge/intel/bd82x6x/chip.h

@@ -4,7 +4,7 @@
 #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
 
 #include <southbridge/intel/common/spi.h>
-#include <stdint.h>
+#include <types.h>
 
 struct southbridge_intel_bd82x6x_config {
 	/**
@@ -58,7 +58,7 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t gen4_dec;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	/* Override PCIe ASPM */
 	uint8_t pcie_aspm[8];

src/southbridge/intel/bd82x6x/pch.c

@@ -319,7 +319,7 @@ static void pch_pcie_enable(struct device *dev)
 		 * or the other devices will not be enumerated by the OS.
 		 */
 		if (!dev->enabled)
-			config->pcie_port_coalesce = 1;
+			config->pcie_port_coalesce = true;
 
 		if (config->pcie_port_coalesce)
 			printk(BIOS_INFO,

src/southbridge/intel/i82801gx/chip.h

@@ -3,7 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 
-#include <stdint.h>
+#include <types.h>
 
 enum sata_mode {
 	SATA_MODE_AHCI = 0,
@@ -61,7 +61,7 @@ struct southbridge_intel_i82801gx_config {
 	uint32_t sata_ports_implemented;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	int c4onc3_enable:1;
 	int docking_supported:1;

src/southbridge/intel/i82801gx/pcie.c

@@ -137,7 +137,7 @@ static void ich_pcie_device_set_func(int index, int pci_func)
 static void root_port_commit_config(struct device *dev)
 {
 	int i;
-	int coalesce = 0;
+	bool coalesce = false;
 
 	if (dev->chip_info != NULL) {
 		const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
@@ -145,7 +145,7 @@ static void root_port_commit_config(struct device *dev)
 	}
 
 	if (!rpc.ports[0]->enabled)
-		coalesce = 1;
+		coalesce = true;
 
 	for (i = 0; i < rpc.num_ports; i++) {
 		struct device *pcie_dev;

src/southbridge/intel/lynxpoint/chip.h

@@ -65,7 +65,7 @@ struct southbridge_intel_lynxpoint_config {
 	uint32_t gen4_dec;
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
+	bool pcie_port_coalesce;
 
 	/* Force root port ASPM configuration with port bitmap */
 	uint8_t pcie_port_force_aspm;

src/southbridge/intel/lynxpoint/pcie.c

@@ -28,7 +28,7 @@ struct root_port_config {
 	u32 b0d28f0_32c;
 	u32 b0d28f4_32c;
 	u32 b0d28f5_32c;
-	int coalesce;
+	bool coalesce;
 	int gbe_port;
 	int num_ports;
 	struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -304,7 +304,7 @@ static void root_port_commit_config(void)
 
 	/* If the first root port is disabled the coalesce ports. */
 	if (!is_rp_enabled(1))
-		rpc.coalesce = 1;
+		rpc.coalesce = true;
 
 	/* Perform clock gating configuration. */
 	pcie_enable_clock_gating();