GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/cezanne/chipset.cb: rename alias for SATA controllers 

Renoir/Cezanne have two SATA controllers with 2 ports each, so call them
sata_0 and sata_1.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-03-02 18:30:33 +01:00
parent edd748fdb3
commit af6a434236
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/cezanne/chipset.cb
View File

@ -32,8 +32,8 @@ chip soc/amd/cezanne
device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
end
device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
device pci 0.0 alias sata_ahci off end # SATA AHCI Mode
device pci 0.1 alias sata_raid off end # SATA Controller; SATA Raid/AHCI Mode
device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
end