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sb/intel/bd82x6x: Use {read,write}32p 

While on it, sort includes.

Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-12-04 09:09:49 +01:00 committed by Felix Held
parent 067642d939
commit af776d8b66
2 changed files with 17 additions and 15 deletions
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19
src/southbridge/intel/bd82x6x/smihandler.c
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@ -1,20 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <commonlib/region.h> #include <commonlib/region.h>
#include <device/pci_def.h> #include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <cpu/x86/smm.h>
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <soc/nvs.h> #include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/bd82x6x/me.h>
#include <southbridge/intel/common/gpio.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/finalize.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmutil.h>
#include <types.h>
#include "pch.h" #include "pch.h"
@ -168,7 +169,7 @@ static void xhci_a0_suspend_smm_workaround(void)
/* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */ /* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */
for (unsigned int port = 0; port < 4; port++) { for (unsigned int port = 0; port < 4; port++) {
if (read32((void *)(xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0)) if (read32p((xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0))
pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2); pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2);
} }

13
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -2,12 +2,13 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
#include <device/pci_ehci.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ehci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci.h>
#include "pch.h"
static void usb_ehci_init(struct device *dev) static void usb_ehci_init(struct device *dev)
{ {
@ -46,8 +47,8 @@ static void usb_ehci_init(struct device *dev)
res = probe_resource(dev, PCI_BASE_ADDRESS_0); res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
/* Number of ports and companion controllers. */ /* Number of ports and companion controllers. */
reg32 = read32((void *)(uintptr_t)(res->base + 4)); reg32 = read32p((uintptr_t)(res->base + 4));
write32((void *)(uintptr_t)(res->base + 4), write32p((uintptr_t)(res->base + 4),
(reg32 & 0xfff00000) | 3); (reg32 & 0xfff00000) | 3);
} }