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AGESA fam12: Fix MMCONF region 

MMIO for non-posted region used hard-coded setting for 64 buses
while MSR programming was for 256 buses.

Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7812
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2014-12-14 16:36:09 +02:00
parent 3787d5b36a
commit af87020f0a
1 changed files with 4 additions and 3 deletions
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7
src/northbridge/amd/agesa/family12/agesawrapper.c
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@ -176,7 +176,7 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
@ -187,7 +187,9 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Enable Non-Post Memory in CPU */
PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
PciData = (PciData >> 8) & ~0xff;
PciData |= 0x80;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@ -198,7 +200,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
/* Enable memory access */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
PciData |= BIT1;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);