soc/intel/skylake: Fix broken GNVS offset for chromeos

Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused
array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/include/soc/nvs.h

@@ -61,7 +61,7 @@ typedef struct {
 	u8	ecps; /* 0x43 - SGX Enabled status */
 	u64	emna; /* 0x44 - 0x4B EPC base address */
 	u64	elng; /* 0x4C - 0x53 EPC Length */
-	u8	unused[189];
+	u8	unused[172];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;