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Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 

This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-15 07:47:51 +00:00
parent e49903650c
commit af8b2b91b4
4 changed files with 0 additions and 19 deletions
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5
src/cpu/intel/slot_1/Kconfig
View File

@ -21,11 +21,6 @@ config CPU_INTEL_SLOT_1
bool
select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
default 0xc0000
depends on CPU_INTEL_SLOT_1
config DCACHE_RAM_SIZE
hex
default 0x01000

5
src/cpu/intel/slot_2/Kconfig
View File

@ -20,11 +20,6 @@
config CPU_INTEL_SLOT_2
bool
config DCACHE_RAM_BASE
hex
default 0xc0000
depends on CPU_INTEL_SLOT_2
config DCACHE_RAM_SIZE
hex
default 0x01000

5
src/cpu/intel/socket_FC_PGA370/Kconfig
View File

@ -26,11 +26,6 @@ config CPU_INTEL_SOCKET_FC_PGA370
select CACHE_AS_RAM
select TINY_BOOTBLOCK
config DCACHE_RAM_BASE
hex
default 0xffdf8000
depends on CPU_INTEL_SOCKET_FC_PGA370
config DCACHE_RAM_SIZE
hex
default 0x8000

4
src/cpu/intel/socket_PGA370/Kconfig
View File

@ -30,10 +30,6 @@ config SSE2
bool
default n
config DCACHE_RAM_BASE
hex
default 0xc0000
config DCACHE_RAM_SIZE
hex
default 0x01000