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mb/pcengines/apu1/platform_cfg.h: Unset UsbRxMode to avoid platform reset issue 

On PC Engines apu1 there were issues with cold reset. Platform hangs
in boot path after performing reset using CF9h.
CB:10549 (amd/sb800: Make UsbRxMode per-board customizable)
mentions a similar issue, and added a configuration macro for it.
That error is also described in AMD SB800 Family Product Errata,
section 15 USB Resets Asynchronously With Port CF9h Hard Reset.

This workaround simply non-execute USB configuration during boot
and hence no reset via CF9h is done.

TEST=perform multiple cold resets and see if platform boots

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Piotr Kleinschmidt 2020-05-21 17:48:12 +02:00 committed by Michał Żygowski
parent be698de76e
commit af90a1e6af
1 changed files with 14 additions and 0 deletions
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14
src/mainboard/pcengines/apu1/platform_cfg.h
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@ -212,4 +212,18 @@
*/ */
#define FADT_PM_PROFILE 1 #define FADT_PM_PROFILE 1
/**
* @def USB_RX_MODE
* 0x00 - leave Cg2Pll voltage at default value (1.222V)
* 0x01 - lower Cg2Pll voltage to 1.1V
*
* Workaround for reset issues via outb(0x6, 0xcf9).
* For details check:
* AMD SB800 Family Product Errata,
* Section 15. USB Resets Asynchronously With Port CF9h Hard Reset
*
*/
#define USB_RX_MODE 0x00
#endif /* _PLATFORM_CFG_H_ */ #endif /* _PLATFORM_CFG_H_ */