resolve conflict
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -7,7 +7,27 @@
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#define GLCP_DELAY_CONTROLS 0x4c00000f
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#define GLCP_SYS_RSTPLL 0x4c000014
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#define GLCP_DOTPLL 0x4c000015
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#define GLCP_CHIP_REVID 0x4c000017
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#define GLCP_CHIP_REVID 0x4c000017
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/* GLCP_SYS_RSTPLL, Upper 32 bits */
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#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
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#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
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#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
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/* GLCP_SYS_RSTPLL, Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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#define GLCP_SYS_RSTPLL_PD 14
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#define GLCP_SYS_RSTPLL_RESETPLL 13
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#define GLCP_SYS_RSTPLL_DDRMODE 10
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#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
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#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
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#define GLCP_SYS_RSTPLL_CHIP_RESET 0
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/* MSR routing as follows*/
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/* MSB = 1 means not for CPU*/
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/* next 3 bits 1st port*/
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@ -272,23 +292,4 @@
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#define VG_GLD_MSR_CONFIG MSR_VG + 0x2001
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#define VG_GLD_MSR_PM MSR_VG + 0x2004
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/* Upper 32 bits */
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#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
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#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
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#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
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/* Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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#define GLCP_SYS_RSTPLL_PD 14
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#define GLCP_SYS_RSTPLL_RESETPLL 13
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#define GLCP_SYS_RSTPLL_DDRMODE 10
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#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
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#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
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#define GLCP_SYS_RSTPLL_CHIP_RESET 0
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#endif /* CPU_AMD_GX2DEF_H */
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