change from AMD for the IRQ10 problem.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -149,7 +149,18 @@ static void msr_init(void)
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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}
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}
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static void gpio_init(void)
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{
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unsigned long m;
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/* Make sure events enable for gpio 12 is off */
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m = inl(GPIOL_EVENTS_ENABLE);
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m &= ~GPIOL_12_SET;
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m |= GPIOL_12_CLEAR;
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outl(m, GPIOL_EVENTS_ENABLE);
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}
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static void main(unsigned long bist)
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static void main(unsigned long bist)
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{
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{
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static const struct mem_controller memctrl [] = {
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static const struct mem_controller memctrl [] = {
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@ -166,6 +177,7 @@ static void main(unsigned long bist)
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* for cs5536
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* for cs5536
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*/
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*/
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cs5536_setup_onchipuart();
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cs5536_setup_onchipuart();
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gpio_init();
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uart_init();
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uart_init();
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console_init();
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console_init();
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@ -276,11 +276,20 @@ static void enable_shadow(device_t dev)
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static void northbridge_init(device_t dev)
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static void northbridge_init(device_t dev)
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{
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{
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unsigned long m;
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struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
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struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
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printk_debug("northbridge: %s()\n", __FUNCTION__);
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printk_debug("northbridge: %s()\n", __FUNCTION__);
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enable_shadow(dev);
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enable_shadow(dev);
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irq_init_steering(dev, nb->irqmap);
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irq_init_steering(dev, nb->irqmap);
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/* HACK HACK HACK HACK */
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/* 0x1000 is where GPIO is being assigned */
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m = inl(0x1038);
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m &= ~GPIOL_12_SET;
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m |= GPIOL_12_CLEAR;
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outl(m, 0x1038);
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}
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}
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/* due to vsa interactions, we need not not touch the nb settings ... */
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/* due to vsa interactions, we need not not touch the nb settings ... */
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