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change from AMD for the IRQ10 problem. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-08-10 03:23:48 +00:00
parent 08af3f535d
commit af9cd4d0cf
2 changed files with 22 additions and 1 deletions
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12
src/mainboard/olpc/rev_a/auto.c
View File

@ -149,6 +149,17 @@ static void msr_init(void)
__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
}
static void gpio_init(void)
{
unsigned long m;
/* Make sure events enable for gpio 12 is off */
m = inl(GPIOL_EVENTS_ENABLE);
m &= ~GPIOL_12_SET;
m |= GPIOL_12_CLEAR;
outl(m, GPIOL_EVENTS_ENABLE);
}
static void main(unsigned long bist)
{
@ -166,6 +177,7 @@ static void main(unsigned long bist)
* for cs5536
*/
cs5536_setup_onchipuart();
gpio_init();
uart_init();
console_init();

9
src/northbridge/amd/gx2/northbridge.c
View File

@ -276,11 +276,20 @@ static void enable_shadow(device_t dev)
static void northbridge_init(device_t dev)
{
unsigned long m;
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
printk_debug("northbridge: %s()\n", __FUNCTION__);
enable_shadow(dev);
irq_init_steering(dev, nb->irqmap);
/* HACK HACK HACK HACK */
/* 0x1000 is where GPIO is being assigned */
m = inl(0x1038);
m &= ~GPIOL_12_SET;
m |= GPIOL_12_CLEAR;
outl(m, 0x1038);
}
/* due to vsa interactions, we need not not touch the nb settings ... */