soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3037,6 +3037,7 @@
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f
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#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186
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#define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80
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#define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80
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/* Intel PCIE device ids */
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/* Intel PCIE device ids */
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@ -3808,6 +3809,7 @@
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#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619
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#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
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#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
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#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
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#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
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/* Intel Northbridge Ids */
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/* Intel Northbridge Ids */
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#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
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#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
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@ -23,6 +23,7 @@ static struct {
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const char *name;
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const char *name;
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} cpu_table[] = {
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} cpu_table[] = {
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{ CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
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{ CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
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{ CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" },
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};
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};
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static struct {
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static struct {
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@ -78,6 +79,7 @@ static struct {
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" },
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{ PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" },
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};
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};
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static struct {
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static struct {
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@ -96,6 +98,7 @@ static struct {
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{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
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{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
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{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
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{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
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};
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};
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static inline uint8_t get_dev_revision(pci_devfn_t dev)
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static inline uint8_t get_dev_revision(pci_devfn_t dev)
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@ -296,6 +296,7 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_ADL_GT1_9,
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PCI_DEVICE_ID_INTEL_ADL_GT1_9,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2,
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PCI_DEVICE_ID_INTEL_ADL_S_GT1,
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PCI_DEVICE_ID_INTEL_ADL_S_GT1,
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PCI_DEVICE_ID_INTEL_ADL_M_GT1,
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0,
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0,
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};
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};
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@ -329,6 +329,7 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31,
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PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32,
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PCI_DEVICE_ID_INTEL_SPR_ESPI_1,
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PCI_DEVICE_ID_INTEL_SPR_ESPI_1,
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0
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0
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};
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};
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