intel/gma: Remove MCH register declarations.
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror. It's not currently used and we don't want any MCH registers in GFX. Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Vladimir Serbinenko
parent
47089f29f0
commit
afc62a7631
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@ -1203,299 +1203,6 @@
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*/
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#define MCHBAR_MIRROR_BASE 0x10000
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#define MCHBAR_MIRROR_BASE_SNB 0x140000
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/** 915-945 and GM965 MCH register controlling DRAM channel access */
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#define DCC 0x10200
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#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
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#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
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#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
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#define DCC_ADDRESSING_MODE_MASK (3 << 0)
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#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
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#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
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/** Pineview MCH register contains DDR3 setting */
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#define CSHRDDR3CTL 0x101a8
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#define CSHRDDR3CTL_DDR3 (1 << 2)
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/** 965 MCH register controlling DRAM channel configuration */
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#define C0DRB3 0x10206
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#define C1DRB3 0x10606
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/** snb MCH registers for reading the DRAM channel configuration */
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#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
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#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
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#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
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#define MAD_DIMM_ECC_MASK (0x3 << 24)
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#define MAD_DIMM_ECC_OFF (0x0 << 24)
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#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
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#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
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#define MAD_DIMM_ECC_ON (0x3 << 24)
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#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
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#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
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#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
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#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
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#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
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#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
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#define MAD_DIMM_A_SELECT (0x1 << 16)
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/* DIMM sizes are in multiples of 256mb. */
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#define MAD_DIMM_B_SIZE_SHIFT 8
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#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
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#define MAD_DIMM_A_SIZE_SHIFT 0
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#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
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/* Clocking configuration register */
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#define CLKCFG 0x10c00
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#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
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#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
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#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
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#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
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#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
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#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
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/* Note, below two are guess */
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#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
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#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
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#define CLKCFG_FSB_MASK (7 << 0)
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#define CLKCFG_MEM_533 (1 << 4)
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#define CLKCFG_MEM_667 (2 << 4)
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#define CLKCFG_MEM_800 (3 << 4)
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#define CLKCFG_MEM_MASK (7 << 4)
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#define TSC1 0x11001
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#define TSE (1<<0)
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#define TR1 0x11006
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#define TSFS 0x11020
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#define TSFS_SLOPE_MASK 0x0000ff00
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#define TSFS_SLOPE_SHIFT 8
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#define TSFS_INTR_MASK 0x000000ff
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#define CRSTANDVID 0x11100
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#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
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#define PXVFREQ_PX_MASK 0x7f000000
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#define PXVFREQ_PX_SHIFT 24
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#define VIDFREQ_BASE 0x11110
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#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
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#define VIDFREQ2 0x11114
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#define VIDFREQ3 0x11118
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#define VIDFREQ4 0x1111c
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#define VIDFREQ_P0_MASK 0x1f000000
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#define VIDFREQ_P0_SHIFT 24
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#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
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#define VIDFREQ_P0_CSCLK_SHIFT 20
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#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
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#define VIDFREQ_P0_CRCLK_SHIFT 16
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#define VIDFREQ_P1_MASK 0x00001f00
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#define VIDFREQ_P1_SHIFT 8
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#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
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#define VIDFREQ_P1_CSCLK_SHIFT 4
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#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
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#define INTTOEXT_BASE_ILK 0x11300
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#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
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#define INTTOEXT_MAP3_SHIFT 24
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#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
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#define INTTOEXT_MAP2_SHIFT 16
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#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
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#define INTTOEXT_MAP1_SHIFT 8
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#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
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#define INTTOEXT_MAP0_SHIFT 0
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#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
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#define MEMSWCTL 0x11170 /* Ironlake only */
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#define MEMCTL_CMD_MASK 0xe000
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#define MEMCTL_CMD_SHIFT 13
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#define MEMCTL_CMD_RCLK_OFF 0
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#define MEMCTL_CMD_RCLK_ON 1
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#define MEMCTL_CMD_CHFREQ 2
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#define MEMCTL_CMD_CHVID 3
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#define MEMCTL_CMD_VMMOFF 4
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#define MEMCTL_CMD_VMMON 5
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#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
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when command complete */
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#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
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#define MEMCTL_FREQ_SHIFT 8
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#define MEMCTL_SFCAVM (1<<7)
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#define MEMCTL_TGT_VID_MASK 0x007f
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#define MEMIHYST 0x1117c
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#define MEMINTREN 0x11180 /* 16 bits */
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#define MEMINT_RSEXIT_EN (1<<8)
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#define MEMINT_CX_SUPR_EN (1<<7)
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#define MEMINT_CONT_BUSY_EN (1<<6)
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#define MEMINT_AVG_BUSY_EN (1<<5)
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#define MEMINT_EVAL_CHG_EN (1<<4)
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#define MEMINT_MON_IDLE_EN (1<<3)
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#define MEMINT_UP_EVAL_EN (1<<2)
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#define MEMINT_DOWN_EVAL_EN (1<<1)
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#define MEMINT_SW_CMD_EN (1<<0)
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#define MEMINTRSTR 0x11182 /* 16 bits */
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#define MEM_RSEXIT_MASK 0xc000
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#define MEM_RSEXIT_SHIFT 14
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#define MEM_CONT_BUSY_MASK 0x3000
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#define MEM_CONT_BUSY_SHIFT 12
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#define MEM_AVG_BUSY_MASK 0x0c00
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#define MEM_AVG_BUSY_SHIFT 10
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#define MEM_EVAL_CHG_MASK 0x0300
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#define MEM_EVAL_BUSY_SHIFT 8
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#define MEM_MON_IDLE_MASK 0x00c0
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#define MEM_MON_IDLE_SHIFT 6
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#define MEM_UP_EVAL_MASK 0x0030
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#define MEM_UP_EVAL_SHIFT 4
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#define MEM_DOWN_EVAL_MASK 0x000c
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#define MEM_DOWN_EVAL_SHIFT 2
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#define MEM_SW_CMD_MASK 0x0003
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#define MEM_INT_STEER_GFX 0
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#define MEM_INT_STEER_CMR 1
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#define MEM_INT_STEER_SMI 2
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#define MEM_INT_STEER_SCI 3
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#define MEMINTRSTS 0x11184
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#define MEMINT_RSEXIT (1<<7)
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#define MEMINT_CONT_BUSY (1<<6)
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#define MEMINT_AVG_BUSY (1<<5)
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#define MEMINT_EVAL_CHG (1<<4)
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#define MEMINT_MON_IDLE (1<<3)
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#define MEMINT_UP_EVAL (1<<2)
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#define MEMINT_DOWN_EVAL (1<<1)
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#define MEMINT_SW_CMD (1<<0)
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#define MEMMODECTL 0x11190
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#define MEMMODE_BOOST_EN (1<<31)
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#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
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#define MEMMODE_BOOST_FREQ_SHIFT 24
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#define MEMMODE_IDLE_MODE_MASK 0x00030000
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#define MEMMODE_IDLE_MODE_SHIFT 16
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#define MEMMODE_IDLE_MODE_EVAL 0
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#define MEMMODE_IDLE_MODE_CONT 1
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#define MEMMODE_HWIDLE_EN (1<<15)
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#define MEMMODE_SWMODE_EN (1<<14)
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#define MEMMODE_RCLK_GATE (1<<13)
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#define MEMMODE_HW_UPDATE (1<<12)
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#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
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#define MEMMODE_FSTART_SHIFT 8
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#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
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#define MEMMODE_FMAX_SHIFT 4
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#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
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#define RCBMAXAVG 0x1119c
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#define MEMSWCTL2 0x1119e /* Cantiga only */
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#define SWMEMCMD_RENDER_OFF (0 << 13)
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#define SWMEMCMD_RENDER_ON (1 << 13)
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#define SWMEMCMD_SWFREQ (2 << 13)
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#define SWMEMCMD_TARVID (3 << 13)
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#define SWMEMCMD_VRM_OFF (4 << 13)
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#define SWMEMCMD_VRM_ON (5 << 13)
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#define CMDSTS (1<<12)
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#define SFCAVM (1<<11)
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#define SWFREQ_MASK 0x0380 /* P0-7 */
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#define SWFREQ_SHIFT 7
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#define TARVID_MASK 0x001f
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#define MEMSTAT_CTG 0x111a0
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#define RCBMINAVG 0x111a0
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#define RCUPEI 0x111b0
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#define RCDNEI 0x111b4
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#define RSTDBYCTL 0x111b8
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#define RS1EN (1<<31)
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#define RS2EN (1<<30)
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#define RS3EN (1<<29)
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#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
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#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
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#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
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#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
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#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
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#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
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#define RSX_STATUS_MASK (7<<20)
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#define RSX_STATUS_ON (0<<20)
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#define RSX_STATUS_RC1 (1<<20)
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#define RSX_STATUS_RC1E (2<<20)
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#define RSX_STATUS_RS1 (3<<20)
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#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
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#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
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#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
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#define RSX_STATUS_RSVD2 (7<<20)
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#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
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#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
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#define JRSC (1<<17) /* rsx coupled to cpu c-state */
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#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
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#define RS1CONTSAV_MASK (3<<14)
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#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
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#define RS1CONTSAV_RSVD (1<<14)
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#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
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#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
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#define NORMSLEXLAT_MASK (3<<12)
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#define SLOW_RS123 (0<<12)
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#define SLOW_RS23 (1<<12)
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#define SLOW_RS3 (2<<12)
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#define NORMAL_RS123 (3<<12)
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#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
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#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
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#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
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#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
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#define RS_CSTATE_MASK (3<<4)
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#define RS_CSTATE_C367_RS1 (0<<4)
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#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
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#define RS_CSTATE_RSVD (2<<4)
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#define RS_CSTATE_C367_RS2 (3<<4)
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#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
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#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
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#define VIDCTL 0x111c0
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#define VIDSTS 0x111c8
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#define VIDSTART 0x111cc /* 8 bits */
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#define MEMSTAT_ILK 0x111f8
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#define MEMSTAT_VID_MASK 0x7f00
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#define MEMSTAT_VID_SHIFT 8
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#define MEMSTAT_PSTATE_MASK 0x00f8
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#define MEMSTAT_PSTATE_SHIFT 3
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#define MEMSTAT_MON_ACTV (1<<2)
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#define MEMSTAT_SRC_CTL_MASK 0x0003
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#define MEMSTAT_SRC_CTL_CORE 0
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#define MEMSTAT_SRC_CTL_TRB 1
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#define MEMSTAT_SRC_CTL_THM 2
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#define MEMSTAT_SRC_CTL_STDBY 3
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#define RCPREVBSYTUPAVG 0x113b8
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#define RCPREVBSYTDNAVG 0x113bc
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#define PMMISC 0x11214
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#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
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#define SDEW 0x1124c
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#define CSIEW0 0x11250
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#define CSIEW1 0x11254
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#define CSIEW2 0x11258
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#define PEW 0x1125c
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#define DEW 0x11270
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#define MCHAFE 0x112c0
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#define CSIEC 0x112e0
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#define DMIEC 0x112e4
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#define DDREC 0x112e8
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#define PEG0EC 0x112ec
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#define PEG1EC 0x112f0
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#define GFXEC 0x112f4
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#define RPPREVBSYTUPAVG 0x113b8
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#define RPPREVBSYTDNAVG 0x113bc
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#define ECR 0x11600
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#define ECR_GPFE (1<<31)
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#define ECR_IMONE (1<<30)
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#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
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#define OGW0 0x11608
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#define OGW1 0x1160c
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#define EG0 0x11610
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#define EG1 0x11614
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#define EG2 0x11618
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#define EG3 0x1161c
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#define EG4 0x11620
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#define EG5 0x11624
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#define EG6 0x11628
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#define EG7 0x1162c
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#define PXW 0x11664
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#define PXWL 0x11680
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#define LCFUSE02 0x116c0
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#define LCFUSE_HIV_MASK 0x000000ff
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#define CSIPLL0 0x12c10
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#define DDRMPLL1 0X12c20
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#define PEG_BAND_GAP_DATA 0x14d68
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#define GEN6_GT_THREAD_STATUS_REG 0x13805c
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#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
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#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
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#define GEN6_GT_PERF_STATUS 0x145948
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#define GEN6_RP_STATE_LIMITS 0x145994
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#define GEN6_RP_STATE_CAP 0x145998
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/*
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* Logical Context regs
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*/
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@ -2942,21 +2649,6 @@
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#define SNB_FIFO_LINE_SIZE 64
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/* the address where we get all kinds of latency value */
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#define SSKPD 0x5d10
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#define SSKPD_WM_MASK 0x3f
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#define SSKPD_WM0_SHIFT 0
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#define SSKPD_WM1_SHIFT 8
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#define SSKPD_WM2_SHIFT 16
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#define SSKPD_WM3_SHIFT 24
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#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
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#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
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#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
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#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
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#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
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/*
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* The two pipe frame counter registers are not synchronized, so
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* reading a stable value is somewhat tricky. The following code
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